Interpolative divider

A method for generating an output clock signal, the method comprising:

• receiving an input clock signal at an interpolative divider;
• dividing the input clock signal in an integer divider according to an integer divider control signal;
• supplying an output of the integer divider to a phase interpolator;
• charging a first capacitor in the phase interpolator using a first current source during a first part of a charging cycle and during a second part of the charging cycle;
• charging a second capacitor in the phase interpolator using a second current source during a second part of a charging cycle but not the first part of the charging cycle;
• and
• generating a transition in the output clock signal from the interpolative divider responsive to a first voltage across the first capacitor and a second voltage across the second capacitor being equal.

A clock generator system comprising:

• a first interpolative divider configured to divide an input clock signal by a first divide ratio, the first interpolative divider including a first integer divider coupled to the input clock signal, the first interpolative divider including a first phase interpolator coupled to the first integer divider to provide a first output clock signal, the first phase interpolator including a first current source coupled to a first capacitor, a second current source coupled to a second capacitor, and a first comparator coupled to the first capacitor and the second capacitor;
• a second interpolative divider to divide the input clock signal by a second divide ratio, independent of the first divide ratio, the second interpolative divider including a second integer divider coupled to the input clock signal, the second interpolative divider including a second phase interpolator coupled to the second integer divider to provide a second output clock signal, the second phase interpolator including a third current source coupled to a third capacitor, a fourth current source coupled to a fourth capacitor, and a second comparator coupled to the first capacitor and the second capacitor;
• and
• a phase-locked loop configured to supply the input clock signal.