US 12,425,023 B2Granted

Semiconductor device

AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation

InventorYosuke Ogasawara

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Abstract

According to one embodiment, a semiconductor device includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first level shifter, and a second level shifter. At a time of outputting a first voltage from a first terminal, a power supply voltage is supplied to the first terminal from the third transistor in accordance with a fourth signal output from the second level shifter, and then the first voltage is supplied to the first terminal from the first transistor in accordance with a second signal output from the first level shifter. At a time of outputting a second voltage from the first terminal, a ground voltage is supplied to the first terminal from the fourth transistor in accordance with the second signal, and then the second voltage is supplied to the first terminal from the second transistor in accordance with the fourth signal.

Claims18

Dependent claims

A semiconductor device comprising:

a first transistor configured to be supplied with a first voltage higher than a power supply voltage and to supply the first voltage to a first terminal;
a second transistor configured to be supplied with a second voltage lower than a ground voltage and to supply the second voltage to the first terminal;
a third transistor configured to be supplied with the power supply voltage and to supply the power supply voltage to the first terminal;
a fourth transistor configured to be supplied with the ground voltage and to supply the ground voltage to the first terminal;
a first level shifter configured to convert the power supply voltage to the first voltage at a time when a first signal is the power supply voltage, and to output a second signal;
and
a second level shifter configured to convert the ground voltage to the second voltage at a time when a third signal is the ground voltage, and to output a fourth signal, wherein
at a time of outputting the first voltage from the first terminal,
the power supply voltage is supplied to the first terminal from the third transistor in accordance with the fourth signal, and then the first voltage is supplied to the first terminal from the first transistor in accordance with the second signal, and
at a time of outputting the second voltage from the first terminal,
the ground voltage is supplied to the first terminal from the fourth transistor in accordance with the second signal, and then the second voltage is supplied to the first terminal from the second transistor in accordance with the fourth signal.

8 more elements

A semiconductor device comprising:

a plurality of switch circuits;
and
a delay circuit configured to delay a plurality of control signals corresponding to the switch circuits, wherein
each of the switch circuits includes:
a first transistor configured to be supplied with a first voltage higher than a power supply voltage and to supply the first voltage to a first terminal;
a second transistor configured to be supplied with a second voltage lower than a ground voltage and to supply the second voltage to the first terminal;
a third transistor configured to be supplied with the power supply voltage and to supply the power supply voltage to the first terminal;
a fourth transistor configured to be supplied with the ground voltage and to supply the ground voltage to the first terminal;
a first level shifter configured to convert the power supply voltage to the first voltage at a time when a first signal is the power supply voltage, and to output a second signal;
and
a second level shifter configured to convert the ground voltage to the second voltage at a time when a third signal is the ground voltage, and to output a fourth signal, wherein
at a time of outputting the first voltage from the first terminal,
the power supply voltage is supplied to the first terminal from the third transistor in accordance with the fourth signal, and then the first voltage is supplied to the first terminal from the first transistor in accordance with the second signal,
at a time of outputting the second voltage from the first terminal,
the ground voltage is supplied to the first terminal from the fourth transistor in accordance with the second signal, and then the second voltage is supplied to the first terminal from the second transistor in accordance with the fourth signal,
the delay circuit includes a first circuit configured to generate a delay signal from the control signals, and a plurality of logical circuits configured to generate the first signal and the third signal by using each of the control signals and the delay signal,
each of the logical circuits is configured to output each of the control signals as one signal of the first signal and the third signal, and
each of the logical circuits is configured to delay each of the control signals by using the delay signal, and to output each of the delayed control signals as the other of the first signal and the third signal.

15 more elements

Dependencies are inferred from the claim text.