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US 12,425,010 B2Granted
Pulse generator and method
AssigneeCypress Semiconductor Corporation
InventorsMarkus Haunschild, Martin Feldtkeller, Lei Liao, Claudio Andreotti
Life of this patent
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Abstract
A pulse generator comprises a circuit configured to generate a coarse pulse width (CPW) signal, a first delay unit configured to generate a first delayed coarse pulse width signal, a delay locked loop circuit configured to generate a first subphase signal and a second subphase signal, a first analog interpolator, a second analog interpolator, and an amplifier having a first input connected to the first analog interpolator and a second input connected to the second analog interpolator and configured to generate a fine pulse width modulation signal.
Claims20
A pulse generator, comprising:
- a circuit configured to generate a coarse pulse width signal based on a digital pulse code;
- a first delay unit configured to generate a first delayed coarse pulse width signal;
- a delay locked loop circuit configured to generate a first subphase signal and a second subphase signal based on a system clock signal;
- a first analog interpolator having a first input generated based on the coarse pulse width signal and the first subphase signal, a second input generated based on the first delayed coarse pulse width signal and the first subphase signal, and an output having a first delay configured based on the digital pulse code;
- a second analog interpolator having a first input generated based on the coarse pulse width signal and the second subphase signal, a second input generated based on the first delayed coarse pulse width signal and the second subphase signal, and an output having a second delay configured based on the digital pulse code;
- and
- an amplifier having a first input connected to the output of the first analog interpolator and a second input connected to the output of the second analog interpolator and configured to generate a fine pulse width modulation signal.
4 more elements
A method, comprising:
- generating a coarse pulse width signal based on a digital pulse code;
- generating a first delayed coarse pulse width signal based on the coarse pulse width signal;
- generating a first subphase signal and a second subphase signal in a delay locked loop circuit based on a system clock signal;
- generating a first output in a first analog interpolator receiving a first input generated based on the coarse pulse width signal and the first subphase signal and a second input generated based on the first delayed coarse pulse width signal and the first subphase signal, the first output having a first delay configured based on the digital pulse code;
- generating a second output in a second analog interpolator receiving a first input generated based on the coarse pulse width signal and the second subphase signal and a second input generated based on the first delayed coarse pulse width signal and the second subphase signal, the second output having a second delay configured based on the digital pulse code;
- and
- generating a fine pulse width modulation signal in an amplifier having a first input connected to the first output of the first analog interpolator and a second input connected to the second output of the second analog interpolator.
4 more elements
A digital controller, comprising:
- an analog-to-digital converter configured to generate a feedback voltage;
- a voltage control unit configured to generate a target voltage;
- a digital compensator configured to receive a voltage error signal based on the feedback voltage and the target voltage and generate a digital pulse code based on the voltage error signal;
- and
- a pulse generator configured to generate a fine pulse width modulation signal based on the digital pulse code, the pulse generator comprising:
- a circuit configured to generate a coarse pulse width signal based on the digital pulse code;
- a first delay unit configured to generate a first delayed coarse pulse width signal;
- a delay locked loop circuit configured to generate a first subphase signal and a second subphase signal based on a system clock signal;
- a first analog interpolator having a first input generated based on the coarse pulse width signal and the first subphase signal, a second input generated based on the first delayed coarse pulse width signal and the first subphase signal, and an output having a first delay configured based on the digital pulse code;
- a second analog interpolator having a first input generated based on the coarse pulse width signal and the second subphase signal, a second input generated based on the first delayed coarse pulse width signal and the second subphase signal, and an output having a second delay configured based on the digital pulse code;
- and
- an amplifier having a first input connected to the output of the first analog interpolator and a second input connected to the output of the second analog interpolator and configured to generate the fine pulse width modulation signal.
9 more elements
Dependencies are inferred from the claim text.