Method and device for outputting frequency multiplication signal having high harmonic suppression, and storage medium

A method for outputting a frequency multiplication signal with high harmonic suppression, comprising:

• obtaining an initial signal;
• inputting the initial signal into a target circuit, wherein the target circuit includes a parallel circuit, a first circuit of the parallel circuit is provided with a frequency multiplier, a second circuit of the parallel circuit is provided with a phase adjustment module, the first circuit is connected to an input end and an output end of the target circuit, the second circuit is disconnected from the input end and the output end, and the phase adjustment module is configured to adjust a phase of the second circuit to a target phase, wherein a phase difference between the target phase and a first phase of the first circuit is more than 90 degrees;
• and
• taking a target signal output from the target circuit as a frequency multiplication signal of the initial signal;
• wherein the phase adjustment module is further configured to set a harmonic amplitude of the second circuit to have a difference less than a first threshold from a harmonic amplitude of the first circuit.