US 12,424,981 B2Granted

Methods and apparatus to reduce error in operational amplifiers

AssigneeTexas Instruments Incorporated

InventorsKunal Karanjkar, Venkata Ramanan R, Srinivasa BS Chakravarthy, Per Torstein Roine

Life of this patent

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Abstract

An example device includes: switch circuitry configured to: connect, in a first state based on a control signal, a first switch input to a first switch output and a second switch input to a second switch output; and connect, in a second state based on the control signal, the first switch input to the second switch output and the second switch input to the first switch output; an operational amplifier configured to: generate, in response to the control signal, a first voltage based on a gain and the connections in the first state; and generate, in response to the control signal, a second voltage based on the gain and the connections in the second state; and an Analog to Digital Converter (ADC) configured to convert the first voltage and the second voltage into a digital value based on a multiplication of the input voltage and the gain.

Claims20

Dependent claims

A device comprising:

an operational amplifier having:
a positive input;
a negative input;
and
an output;
switch circuitry having:
a first switch input configured to receive an input voltage;
a first switch output coupled to the positive input of the operational amplifier;
a second switch input coupled to the output of the operational amplifier;
and
a second switch output coupled to the negative input of the operational amplifier;
wherein the switch circuitry is configured to:
electrically couple, in a first state specified by a control signal, the first switch input to the first switch output and the second switch input to the second switch output;
and
electrically couple, in a second state specified by the control signal, the first switch input to the second switch output and the second switch input to the first switch output;
and
wherein the operational amplifier is configured to:
generate a first voltage the switch circuitry in the first state;
and
generate a second voltage using the switch circuitry in the second state;
and
an Analog to Digital Converter (ADC) having:
sample-and-hold circuitry coupled to the output of the operational amplifier;
and
control circuitry coupled to the sample-and-hold circuitry and configured to provide the control signal specifying either the first state or the second state based on the sample-and-hold circuitry;
wherein the ADC is configured to convert the first voltage and second voltage into a digital value.

23 more elements

A device comprising:

an operational amplifier having:
a positive input;
a negative input;
and
an output;
switch circuitry having:
a first switch input coupled to receive an input voltage;
a first switch output coupled to the positive input of the operational amplifier;
a second switch input coupled to the output of the operational amplifier;
and
a second switch output coupled to the negative input of the operational amplifier;
wherein the switch circuitry is configured to:
electrically connect, in a first state based on a control signal, the first switch input to the first switch output and the second switch input to the second switch output;
and
electrically connect, in a second state based on the control signal, the first switch input to the second switch output and the second switch input to the first switch output;
wherein the operational amplifier is configured to:
generate, in response to the control signal, a first voltage;
and
generate, in response to the control signal, a second voltage;
and
an Analog to Digital Converter (ADC) having:
an input coupled to the operational amplifier;
a first output coupled to a memory;
and
a second output coupled to the switch circuitry and configured to provide the control signal;
wherein the ADC is configured to:
convert the first voltage and second voltage into a digital value;
store the digital value in the memory;
and
cause the control signal to alternate between indicating the first state and indicating the second state at a frequency determined by the ADC;
and
processor circuitry having an input coupled to the memory and configured to perform an action based on the digital value.

29 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/897,958Filed 29 Aug 2022
Priority: IN 20224101779428 Mar 2022
Published: US 2023/0308055 A128 Sep 2023
Granted: 23 Sep 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03F 1/26
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements: modifications of…
H03F 1/304
Using a switching device: and using digital means
H03F 3/187
With semiconductor devices only: in integrated circuits
H03F 3/393
With semiconductor devices only: with field-effect devices