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US 12,424,559 B2Granted
Package with a substrate comprising embedded escape interconnects and surface escape interconnects
AssigneeQUALCOMM Incorporated
InventorsKuiwon Kang, Hong Bok We, Michelle Yejin Kim
Life of this patent
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Abstract
A package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer, and a plurality of interconnects comprising a plurality of escape interconnects. The plurality of escape interconnects includes a first embedded escape interconnect, a second embedded escape interconnect, and a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect.
Claims23
A package comprising:
- a substrate comprising:
- at least one dielectric layer;
- a solder resist layer coupled to and touching a surface of the at least one dielectric layer;
- and
- a plurality of interconnects comprising a plurality of escape interconnects, wherein the plurality of escape interconnects comprises:
- a first embedded escape interconnect located at least partially in the at least one dielectric layer, wherein the first embedded escape interconnect touches the solder resist layer, wherein the first embedded escape interconnect comprises a first embedded escape pad and a first embedded trace;
- a second embedded escape interconnect located at least partially in the at least one dielectric layer, wherein the second embedded escape interconnect touches the solder resist layer, wherein the second embedded escape interconnect comprises a second embedded escape pad and a second embedded escape trace;
- and
- a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect,
- wherein the third escape interconnect is located on the surface of the at least one dielectric layer that touches the solder resist layer,
- wherein a side surface of the third escape interconnect touches the solder resist layer, and
- wherein the third escape interconnect comprises a first surface escape pad and a first surface escape trace;
- a first integrated device coupled to the substrate;
- and
- a second integrated device coupled to the substrate.
12 more elements
A package comprising:
- a substrate comprising:
- at least one dielectric layer;
- a solder resist layer coupled to and touching a surface of the at least one dielectric layer;
- means for first embedded escape interconnection located at least partially in the at least one dielectric layer, wherein the means for first embedded escape interconnection touches the solder resist layer, wherein the means for first embedded escape interconnection comprises a first embedded escape pad and a first embedded trace;
- means for second embedded escape interconnection located at least partially in the at least one dielectric layer, wherein the means for second embedded escape interconnection touches the solder resist layer, wherein the means for second embedded escape interconnection comprises a second embedded escape pad and a second embedded escape trace;
- and
- means for surface escape interconnection, wherein the means for surface escape interconnection is located between the means for first embedded escape interconnection and the means for second embedded escape interconnection,
- wherein the means for surface escape interconnection is located on the surface of the at least one dielectric layer that touches the solder resist layer,
- wherein a side surface of the means for surface escape interconnection touches the solder resist layer, and
- wherein the means for surface escape interconnection comprises a first surface escape pad and a first surface escape trace;
- a first integrated device coupled to the substrate;
- and
- a second integrated device coupled to the substrate.
10 more elements
A method for fabricating a package, comprising:
- providing a substrate comprising:
- at least one dielectric layer;
- and
- a solder resist layer coupled to and touching a surface of the at least one dielectric layer;
- and
- a plurality of interconnects comprising a plurality of escape interconnects, wherein the plurality of escape interconnects comprises:
- a first embedded escape interconnect located at least partially in the at least one dielectric layer, wherein the first embedded escape interconnect touches the solder resist layer;
- a second embedded escape interconnect located at least partially in the at least one dielectric layer, wherein the second embedded escape interconnect touches the solder resist layer;
- and
- a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect,
- wherein the third escape interconnect is located on the surface of the at least one dielectric layer that touches the solder resist layer,
- wherein a side surface of the third escape interconnect touches the solder resist layer,
- wherein a portion of the third escape interconnect is located parallel to a portion of the first embedded escape interconnect and a portion of the second embedded escape interconnect,
- wherein the third escape interconnect is located on a different metal layer than the first embedded escape interconnect and the second embedded escape interconnect,
- wherein the third escape interconnect is directly adjacent to the first embedded escape interconnect, and
- wherein the third escape interconnect is directly adjacent to the second embedded escape interconnect;
- coupling a first integrated device to the substrate;
- and
- coupling a second integrated device to the substrate.
16 more elements
Dependencies are inferred from the claim text.