Control circuit, memory system and control method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWin-San Khwa, Jen-Chieh Liu, Meng-Fan Chang, Tung-Ying Lee, Jin Cai
Life of this patent
Estimating the term…
Abstract
A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.
Claims20
A control circuit, configured to control a plurality of memory cells of a memory array, the control circuit comprising:
- a program controller, configured to:
- program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type,
- wherein a first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is positively correlated to error tolerance of the first bit of a data type,
- wherein error tolerance of the first bit of the data type is an upper bound of error injected into the first bit of the data type that causes accuracy degradation less than a predetermined threshold.
A memory system, comprising:
- a memory array, comprising a plurality of memory cells;
- a control circuit, comprising:
- a write driver, coupled to the memory cells;
- and
- a program controller, coupled to the write driver, the program controller configured to:
- programming, through the write driver, a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type,
- wherein a first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is positively correlated to error tolerance of the first bit of a data type
- wherein error tolerance of the first bit of the data type is an upper bound of error injected into the first bit of the data type that causes accuracy degradation less than a predetermined threshold.
A control method for controlling a plurality of memory cells of a memory array, the control method comprising:
- programming a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type,
- wherein a first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is positively correlated to error tolerance of the first bit of a data type,
- wherein error tolerance of the first bit of the data type is an upper bound of error injected into the first bit of the data type that causes accuracy degradation less than a predetermined threshold.
Dependencies are inferred from the claim text.