One-time programmable (ROTP) NVM

A circuit comprising:

• a plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell comprising first and second bit line terminals coupled to associated bit lines of a plurality of bit lines, and a gate terminal coupled to an associated word line of a plurality of word lines, wherein each word line of the plurality of word lines is coupled to the gate terminals of the transistor-based memory cells of an associated row;
• and
• a controller configured to:
• cause a programing pulse to be provided to a first word line coupled to a first transistor-based memory cell of the plurality of transistor-based memory cells to write a first write value to the first transistor-based memory cell,
• cause a first bit value to be read from the first transistor-based memory cell via a first bit line of the plurality of bit lines,
• cause redundant bit values to be read from redundant transistor-based memory cells of the plurality of transistor-based memory cells, wherein the redundant transistor-based memory cells are configured to store the same value as the first transistor-based memory cell,
• when one of the first bit value and the redundant bit values does not match the first write value, determine a majority bit value based on the first bit value and the redundant bit values read from the redundant transistor-based memory cells, and
• when the majority bit value does not match the first write value, cause a flag signal indicative of a failed programing of the first transistor-based memory cell to the first write value to be asserted.

A non-volatile memory comprising:

• a one-time programmable (OTP) memory sector comprising a first plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell comprising first and second bit line terminals coupled to associated bit lines of a plurality of bit lines, and a gate terminal coupled to an associated word line of a plurality of word lines, wherein each word line of the plurality of word lines is coupled to the gate terminals of the transistor-based memory cells of an associated row;
• and
• a controller configured to:
• cause a programing pulse to be provided to a first word line coupled to a first transistor-based memory cell of the plurality of transistor-based memory cells to write a first write value to the first transistor-based memory cell,
• cause a first bit value to be read from the first transistor-based memory cell via a first bit line of the plurality of bit lines,
• cause redundant bit values to be read from redundant transistor-based memory cells of the plurality of transistor-based memory cells, wherein the redundant transistor-based memory cells are configured to store the same value as the first transistor-based memory cell,
• when one of the first bit value and the redundant bit values does not match the first write value, determine a majority bit value based on the first bit value and the redundant bit values read from the redundant transistor-based memory cells, and
• when the majority bit value does not match the first write value, cause a flag signal indicative of a failed programing of the first transistor-based memory cell to the first write value to be asserted.