Memory cell including programmable resistors with transistor components

A system, comprising:

• a memory cell including:
• a first programmable resistor comprising a first source/drain structure and a second source/drain structure;
• a second programmable resistor comprising a third source/drain structure and a fourth source/drain structure;
• and
• a control transistor coupled to the first source/drain structure of the first programmable resistor and to the third source/drain structure of the second programmable resistor;
• and
• a memory controller coupled to the memory cell and configured to:
• apply a first voltage to a gate structure of the first programmable resistor to set the first programmable resistor to have a first resistance, in response to the control transistor being enabled, thereby programming the memory cell with a first logic value;
• and
• apply the first voltage to a gate structure of the second programmable resistor to set the second programmable resistor to have the first resistance, with the control transistor being enabled, thereby programming the memory cell with a second logic value.

A memory system, comprising:

• a memory cell including:
• a first programmable resistor comprising a first source/drain structure and a second source/drain structure;
• a second programmable resistor comprising a third source/drain structure and a fourth source/drain structure;
• and
• a control transistor coupled to the first source/drain structure of the first programmable resistor and to the third source/drain structure of the second programmable resistor;
• and
• a memory controller coupled to the memory cell and configured to:
• apply a first voltage to a gate structure of the first programmable resistor to set the first programmable resistor to have a first resistance, in response to the control transistor being enabled, thereby programming the memory cell with a first logic value;
• and
• apply the first voltage to a gate structure of the second programmable resistor to set the second programmable resistor to have the first resistance, with the control transistor being enabled, thereby programming the memory cell with a second logic value;
• wherein the second source/drain structure of the first programmable resistor is electrically floating, and the fourth source/drain structure of the second programmable resistor is electrically floating.