Integrated chiplet-based central processing units with accelerators

A method comprising:

• generating, at an accelerator, a uniform memory access tunneling packet protocol structure that maps to a die-to-die interconnect;
• utilizing, at the accelerator, the uniform memory access tunneling packet structure to generate a uniform memory access tunneling packet, the uniform memory access tunneling packet being used to tunnel a high-level interconnect protocol into a die-to-die interconnect protocol associated with the die-to-die interconnect, the accelerator utilizes a uniform memory access tunneling system located in the accelerator to facilitate the tunnel of the high-level interconnect protocol, wherein the uniform memory access tunneling packet encapsulates high-level interconnect protocol information in additional tunneling fields added to a die-to-die interface packet structure associated with the die-to-die interconnect;
• and
• utilizing the uniform memory access tunneling packet to direct access to uniform memory.

A server system comprising:

• an accelerator interface controller;
• a die-to-die interconnect coupled to the accelerator interface controller;
• and
• a central processing unit (CPU) interface controller coupled to the die-to-die interconnect, wherein the accelerator interface controller is configured to utilize a uniform memory access tunneling system located in the accelerator interface controller to tunnel a high-level interconnect protocol into a die-to-die interconnect protocol associated with the die-to-die interconnect in order to access a uniform memory, wherein the CPU interface controller is configured to receive a uniform memory access tunneling packet that encapsulates high-level interconnect protocol information in additional tunneling fields added to a die-to-die interface packet structure associated with the die-to-die interconnect.