Code generation based on processor usage
AssigneeNVIDIA Corporation
InventorsJaydeep Marathe, Michael Murphy, Xiaohua Zhang
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Abstract
Apparatuses, systems, and techniques to generate code to be performed by one or more first processors based, at least in part, on one or more indications of data to be used by one or more second processors. In at least one embodiment, a CUDA program includes host code and device code, and a linker uses references for code elements in host code to link or prune code elements from device code.
Claims39
One or more processors comprising:
- processing circuitry to:
- generate first device code by removing one or more code elements from second device code based on reference information, in host code, indicating one or more code elements that are not to be performed.
A system, comprising one or more processors and memory to store instructions that, as a result of execution by one or more processors, cause the one or more processors to:
- generate first device code, by removing one or more code elements from second device code based on reference information, in host code, indicating one or more code elements that are not to be executed.
A non-transitory machine-readable medium having stored thereon one or more instructions, which if performed by one or more processors, cause one or more processors to at least:
- generate first device code, by removing one or more code elements from second device code based on reference information, in host code, indicating one or more code elements that are not to be performed.
A method comprising:
- generating first device code by removing one or more code elements from second device code based on reference information, in host code, indicating one or more code elements that are not to be performed.
Dependencies are inferred from the claim text.