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US 12,423,056 B2Granted
Multiply-accumulate unit
AssigneeAnaflash Inc.
InventorsSeung-Hwan Song, Sang-Soo Lee, Sihwan Kim
Life of this patent
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Abstract
An analog multiplier accumulator array comprises analog multipliers organized in a matrix of rows and columns, each of the multiplier comprising one or more than one analog input signal line coupled to the analog multipliers in a row of the array; an analog level sensing circuit; a set of bit lines, each bit line electrically connected to the analog multiplier in each column of the row; and an analog accumulator configured to connect the set of the bit lines to an analog level sensing circuit for generating digital output signals, wherein an access transistor connected to the analog input line and a variable resistor form the analog multiplier.
Claims17
An analog multiplier accumulator array, comprising:
- analog multipliers organized in a matrix of rows and columns,
- one or more than one analog input signal line coupled to an analog multiplier in a row of the array;
- an analog level sensing circuit;
- a set of one or more than one bit line, each bit line electrically connected to an analog multiplier in each column of the row;
- and
- an analog accumulator configured to connect the set of bit line to the analog level sensing circuit configured to generate digital output signals,
- wherein each analog multiplier comprises an access transistor connected to the analog input signal line and a variable resistor;
- and
- wherein the analog accumulator comprises:
- an array of metal-oxide semiconductor (MOS) transistors in a row, each MOS transistor connected to a bit line in the set of bit lines;
- and
- one control line, connected to respective gates of the MOS transistors, configured to activate the MOS transistors such that current flowing in the bit lines connected to the MOS transistors are allowed to be merged in one of the connected bit lines when the MOS transistors are activated.
9 more elements
An analog multiplier accumulator array, comprising:
- analog multipliers organized in a matrix of rows and columns,
- one or more than one analog input signal line coupled to an analog multiplier in a row of the array;
- an analog level sensing circuit;
- a plurality of bit lines, each bit line connected to an analog multiplier in each column of the row;
- and
- an analog accumulator configured to connect the plurality of bit lines to the analog level sensing circuit configured to generate digital output signals,
- wherein the analog accumulator comprises a plurality of current mirrors, each of the current mirrors comprising:
- a reference p-channel metal-oxide semiconductor (PMOS) transistor comprising a source terminal connected to a voltage supply, a gate terminal connected to a common gate node connected to one of the bit lines, a drain terminal connected to the common gate node,
- a drive PMOS transistor comprising a source terminal connected to the voltage supply, a gate terminal connected to the common gate node, a drain terminal directly connected to a common output node;
- and
- wherein a plurality of drain terminals of the drive PMOS transistors are directly connected to the common output node, allowing amplified currents from the drive PMOS transistors to be merged on the common output node.
8 more elements
An analog multiplier accumulator array, comprising:
- analog multipliers organized in a matrix of rows and columns;
- a pair of analog input signal lines coupled to an analog multiplier in a row of the array;
- an analog level sensing circuit;
- a set of bit lines, each bit line electrically connected to an analog multiplier in each column of the row;
- and
- an analog accumulator configured to connect the set of the bit lines to the analog level sensing circuit configured to generate a digital output signal,
- wherein each analog multiplier comprises one pair of differential transistors, a variable resistor, and a switching transistor;
- and
- wherein said analog accumulator comprises:
- an array of metal-oxide semiconductor (MOS) transistors in a row, each MOS transistor connected to a bit line in the set of bit lines;
- and
- one control line, connected to respective gates of the MOS transistors, configured to activate the MOS transistors such that current flowing in the bit lines connected to the MOS transistors are allowed to be merged in one of the connected bit lines when the MOS transistors are activated.
9 more elements
An analog multiplier accumulator array, comprising:
- analog multipliers organized in a matrix of rows and columns;
- a pair of analog input signal lines coupled to an analog multiplier in a row of the array;
- an analog level sensing circuit;
- a set of bit lines, each bit line electrically connected to an analog multiplier in each column of the row;
- and
- an analog accumulator configured to connect the set of the bit lines to the analog level sensing circuit configured to generate a digital output signal,
- wherein each analog multiplier comprises one pair of differential transistors, a variable resistor, and a switching transistor;
- wherein the analog accumulator comprises a plurality of current mirrors, each of the current mirrors comprising:
- a reference p-channel metal oxide semiconductor (PMOS) transistor comprising a source terminal connected to a voltage supply, a gate terminal connected to a common gate node connected to one of the set of bit lines, a drain terminal connected to the common gate node,
- a drive PMOS transistor comprising a source terminal connected to the voltage supply, a gate terminal connected to the common gate node, a drain terminal connected to a common output node;
- and
- wherein a plurality of drain terminals of the drive PMOS transistors are directly connected to the common output node, allowing amplified currents from the drive PMOS transistors to be merged on the common output node.
9 more elements
Dependencies are inferred from the claim text.