Source electrode and drain electrode protection for nanowire transistors

A computing device, comprising:

• a processor;
• and
• a memory device laterally separated from the processor, wherein the memory device or the processor includes a nanowire transistor comprising:
• a substrate;
• a channel region including a nanowire above the substrate;
• a metallic source electrode and a metallic drain electrode above the substrate, wherein the metallic source electrode is laterally separated from a first end of the nanowire by a first semiconductor layer between the metallic source electrode and the nanowire, the first semiconductor layer having an uppermost surface co-planar with an uppermost surface of the metallic source electrode, and the metallic drain electrode is laterally separated from a second end of the nanowire by a second semiconductor layer between the metallic drain electrode and the nanowire, the second semiconductor layer having an uppermost surface co-planar with an uppermost surface of the metallic drain electrode;
• a gate electrode over and around the nanowire, the gate electrode having a lateral width between the metallic source electrode and the metallic drain electrode that is greater than a lateral width of the nanowire between the metallic source electrode and the metallic drain electrode;
• a first spacer above the substrate between the gate electrode and the metallic source electrode, a second spacer above the substrate between the gate electrode and the metallic drain electrode;
• and
• a gate dielectric layer between the channel region and the gate electrode.