Capacitor weighted segmentation buffer

A capacitor weighted segmentation buffer comprising:

• a push-pull buffer circuit, comprising:
• a first transistor, having a control terminal, a first connection terminal, and a second connection terminal;
• and
• a second transistor, having a control terminal, a first connection terminal, and a second connection terminal, wherein the second connection terminal of the first transistor and the second connection terminal of the second transistor are source terminals coupled to an output node of the capacitor weighted segmentation buffer;
• and
• a plurality of capacitors, comprising:
• a first capacitor, having a first terminal coupled to the control terminal of the first transistor, and a second terminal arranged to receive a first input signal of the capacitor weighted segmentation buffer;
• a second capacitor, having a first terminal coupled to the control terminal of the second transistor, and a second terminal arranged to receive the first input signal of the capacitor weighted segmentation buffer;
• a third capacitor, having a first terminal coupled to the control terminal of the first transistor, and a second terminal arranged to receive a second input signal of the capacitor weighted segmentation buffer;
• and
• a fourth capacitor, having a first terminal coupled to the control terminal of the second transistor, and a second terminal arranged to receive the second input signal of the capacitor weighted segmentation buffer;
• wherein each of the first capacitor and the second capacitor has a first capacitance value, and each of the third capacitor and the fourth capacitor has a second capacitance value different from the first capacitance value.