Semiconductor packages using package in package systems and related methods
AssigneeSemiconductor Components Industries, LLC
InventorsInpil Yoo, Maria Cristina Estacio, Jerome Teysseyre, Seungwon Im, Jooyang Eom
Life of this patent
Estimating the term…
Abstract
Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.
Claims20
A semiconductor package comprising:
- a metal layer;
- two or more die, each of the two more die coupled to the metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes;
- a first interconnect layer coupled at a source of each of the two more die;
- a second interconnect layer coupled to a gate of each of the two or more die;
- and
- an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, the metal layer, and the second interconnect layer;
- wherein each drain of the two or more die faces towards the metal layer.
A semiconductor package comprising:
- two or more encapsulated die assemblies, each encapsulated die assembly comprising:
- two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die;
- a first interconnect layer coupled at a source of each of the two more die;
- a second interconnect layer electrically coupled to a gate of each of the two or more die;
- and
- an encapsulant surrounding the two or more die and at least a portion of the first interconnect layer, the metal layer, and the second interconnect layer;
- and
- one of a substrate or a leadframe coupled to the two or more encapsulated die assemblies.
A method of forming a semiconductor package, the method comprising:
- providing two or more die;
- coupling each of the two or more die to a metal layer at a drain of each of the two or more die, the two or more die and each metal layer arranged in two parallel planes;
- forming a first interconnect layer coupled to a source of each of the two or more die;
- encapsulating the two or more die, at least a portion of the first interconnect layer, and at least a portion of the metal layer with an encapsulant using one of a transfer molding or laminating process;
- and
- forming a second interconnect layer coupled to a gate of each of the two or more die;
- wherein the drain of each of the two or more die face the metal layer.
Dependencies are inferred from the claim text.