Stacked 3D memory architecture for power optimization

A method comprising:

• providing a 3D stacked memory configured to store image data captured by a camera, the 3D stacked memory comprising a plurality of first drivers/receivers and a plurality of memory banks that are accessible by a plurality of channels in parallel, wherein each memory bank is accessible via a corresponding first driver/receiver;
• and
• providing a System-on-Chip (SoC) configured to process the image data stored in the 3D stacked memory, the SoC comprising a memory controller with a plurality of second drivers/receivers, wherein the plurality of the second drivers/receivers are respectively connected to the plurality of the first drivers/receivers of the 3D stacked memory by the plurality of the channels,
• wherein:
• the SoC and the 3D stacked memory are vertically stacked together;
• the plurality of memory banks each has a page size of 512 bytes or less;
• the plurality of memory banks include at least eight memory banks;
• and
• the plurality of the channels are controlled by a plurality of unidirectional and/or bidirectional links.