Memory device including error correction device

A memory device comprising:

• a memory cell area including a plurality of cell blocks divided into a plurality of normal cell blocks, at least one error correction code (ECC) cell block, and at least one redundancy cell block, the plurality of cell blocks being configured to output data and error correction codes;
• an error correction circuit including a plurality of code calculation circuits corresponding to the cell blocks and configured to generate error-corrected data by correcting errors in the data using the error correction codes while performing, according to second repair control information, a zero-padding operation on a result of calculating on a part of the data by any one of the code calculation circuits;
• and
• a first switch group disposed between the error correction circuit and data pads, configured to output the error-corrected data through the data pads while performing, according to first repair control information, a shifting operation on the error-corrected data.

A memory device comprising:

• a shifting circuit configured to receive user data pieces through data pads from an external device to shift the user data pieces;
• a zero-padding circuit configured to generate a zero-padded data piece;
• an error-correcting circuit configured to generate an error correction code (ECC) data piece for the zero-padded data piece and the shifted user data pieces;
• a swapping circuit configured to swap, with each other, the ECC data piece and the shifted user data piece to be stored in neighboring two among memory blocks;
• and
• the memory blocks arranged in a row and configured to store therein the zero-padded data piece, the shifted user data pieces and the ECC data piece, the memory blocks including a column-repaired memory block that the zero-padded data piece is to be stored in and a redundancy memory block that one of the shifted user data pieces corresponding to the column-repaired memory block is to be stored in,
• wherein the shifting circuit is disposed between the error-correcting circuit and data pads, and the zero-padding circuit is disposed between the memory blocks and the error-correcting circuit.