Memory device for outputting test results
AssigneeSamsung Electronics Co., Ltd.
InventorJongpil Son
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array and a repair circuit configured to perform a repair operation and output a dirty signal to an external destination external to the memory device. The repair circuit further performs selecting a first redundancy address of the redundancy memory cells instead of a first fail address of the first failed memory cell, storing a first redundancy mapping for the first fail address to the first redundancy address, and in response to determining a second fail address of a second failed memory cell matches the first fail address, ignoring the first redundancy mapping, and outputting a dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.
Claims20
A memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged at intersections of a plurality of rows, and a plurality of columns and redundancy memory cells configured to repair a failed memory cell from among the memory cells;
- and
- a repair circuit configured to perform a repair operation on the failed memory cell, and output a dirty signal to an external destination external to the memory device, the repair operation including,
- selecting a first redundancy address of the redundancy memory cells instead of a first fail address of a first failed memory cell,
- storing a first redundancy mapping for the first fail address to the first redundancy address, and,
- in response to determining a second fail address of a second failed memory cell matches the first redundancy address,
- ignoring the first redundancy mapping, and
- outputting the dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.
A memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged at intersections of a plurality of rows and a plurality of columns, and redundancy memory cells configured to repair a failed memory cell from among the plurality of memory cells;
- and
- a repair circuit configured to,
- perform a repair operation on the failed memory cell, and output an overflow flag signal to an external destination external to the memory device, the repair operation including,
- selecting a first redundancy address of the redundancy memory cells instead of a first fail address of a first failed memory cell from among the plurality of memory cells,
- storing a first redundancy mapping for the first fail address to the first redundancy address, and
- outputting the overflow flag signal indicating that a storage space to store a second redundancy mapping for a second fail address of a second failed memory cell from among the plurality of memory cells to a second redundancy address is insufficient.
A memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged at intersections of a plurality of rows and a plurality of columns, and a plurality of redundancy memory cells configured to repair a failed memory cell from among the plurality of memory cells;
- and
- a repair circuit configured to,
- perform a memory test operation on the memory cell array after performing a repair operation on the failed memory cell with a first redundancy memory cell of the plurality of redundancy memory cells, and
- output a first signal to an external destination external to the memory device, the first signal being obtained as a result of the memory test operation and indicating failure of the first redundancy memory cell.
Dependencies are inferred from the claim text.