Clock duty cycle adjustment and calibration circuit and method of operating same

A clock duty cycle adjustment and calibration circuit comprising:

• a clock circuit having a set of stages, the clock circuit configured to generate a first set of phase clock signals having a first duty cycle;
• a set of level shifters configured to output a second set of phase clock signals, each level shifter of the set of level shifters being coupled to a corresponding stage of the set of stages of the clock circuit, each level shifter of the set of level shifters configured to output a corresponding phase clock signal of the second set of phase clock signals based on a corresponding phase clock signal of the first set of phase clock signals;
• a duty cycle adjustment circuit coupled to the set of level shifters, and being configured to:
• generate a first clock output signal responsive to at least a multiplexed selection signal, the first clock output signal having a duty cycle;
• and
• adjust at least the duty cycle responsive to at least a set of control signals or a phase difference between a first phase clock signal of the second set of phase clock signals and a second phase clock signal of the second set of phase clock signals;
• and
• a duty cycle calibration circuit configured to perform a calibration of the duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the calibration of the duty cycle of the first clock output signal.

A method of operating a clock duty cycle adjustment and calibration circuit, the method comprising:

• generating, by a set of level shifters, a first set of phase clock signals having a first duty cycle, each phase clock signal of the first set of phase clock signals being generated by a corresponding level shifter of the set of level shifters;
• generating, by a duty cycle adjustment circuit, a first clock output signal responsive to a first phase clock signal of the first set of phase clock signals and a second phase clock signal of the first set of phase clock signals, the first clock output signal having a second duty cycle;
• and
• adjusting, by the duty cycle adjustment circuit, the first clock output signal responsive to at least a set of control signals, thereby generating an adjusted first clock output signal having an adjusted second duty cycle, wherein adjusting the first clock output signal comprises:
• selecting, by a multiplexer, the second phase clock signal of the first set of phase clock signals as a first input to an edge triggered circuit, the multiplexer being directly coupled to the edge triggered circuit.