Templatized memory pattern generator and method

A templatized memory pattern generator, comprising a test processor (4), a simple memory pattern generator (6), a channel timing & formatter (11), and a pin electronic (12), wherein the test processor (4) comprises a timing generator (1), a pattern generator (2), a simple memory pattern generator (SMPG) control instruction generator (3), a pattern memory, and a memory control;

• the memory control is respectively connected to the timing generator (1), the pattern generator (2), the SMPG control instruction generator (3), and the pattern memory;
• the pattern generator (2) is respectively connected to the timing generator (1) and the SMPG control instruction generator (3);
• the test processor (4) sends a control instruction to the simple memory pattern generator (6);
• the simple memory pattern generator (6) comprises an X address generator (7), a Y address generator (8), a D data generator (9), and an SMPG and channel mapping (10);
• the SMPG and channel mapping (10) are respectively connected to the X address generator (7), the Y address generator (8), and the D data generator (9);
• the X address generator (7) is connected to the Y address generator (8);
• an input terminal of the channel timing & formatter (11) is connected to the SMPG and channel mapping (10);
• an output terminal of the channel timing & formatter (11) is connected to the pin electronic (12);
• the X address generator (7) is composed of an arithmetic logic unit ALU and a 16-bit wide X address register;
• the Y address generator (8) is composed of an arithmetic logic unit ALU and a 16-bit wide Y address register;
• the D data generator (9) is composed of an arithmetic logic unit ALU and a 16-bit wide D address register;
• the X address register comprises an X address preset value register Preset, an X address constant register Const, and an X address enable register Enable;
• a calculation result of the X address generator (7) is controlled by an instruction obtained by the arithmetic logic unit ALU of the X address generator and the X address preset value register Preset, the X address constant register Const, and the X address enable register Enable;
• the Y address register comprises a Y address preset value register Preset, a Y address constant register Const, and a Y address enable register Enable;
• a calculation result of the Y address generator (8) is controlled by an instruction obtained by the arithmetic logic unit ALU of the Y address generator and the Y address preset value register Preset, the Y address constant register Const, and the Y address enable register Enable;
• the D address register comprises a D address preset value register Preset, a D address constant register Const, and a D address enable register Enable;
• a calculation result of the D data generator (9) is controlled by an instruction obtained by the arithmetic logic unit ALU of the D data generator and the D address preset value register Preset, the D address constant register Const, and the D address enable register Enable;
• and
• parallel data calculated by the simple memory pattern generator (6) based on an SMPG resource mapping table provided by an upper computer is mapped to pins of a device under test one by one.