Array substrate and method of manufacturing the same, and display panel

An array substrate, comprising:

• a base substrate;
• a drive circuit layer, disposed on one side of the base substrate and comprising a switching transistor;
• an insulating material layer, disposed on one side of the drive circuit layer distal to the base substrate, and having a connection via-hole exposing at least a part region of a drain electrode of the switching transistor;
• and
• an electrode layer, disposed on one side of the insulating material layer distal to the base substrate, wherein a surface of the electrode layer distal to the base substrate has at least one groove structure extending to the connection via-hole;
• wherein the electrode layer comprises a second electrode layer;
• and
• an opening of the connection via-hole is in a circular shape and the opening close to the base substrate has a diameter of 7 to 8 microns, and
• the second electrode layer has a common electrode and covers the connection via-hole, the second electrode layer comprises a plurality of strip sub-electrodes, slits located among the strip sub-electrodes, and drainage grooves serving as the groove structures, wherein the strip sub-electrode has a width of 2.5 to 3.5 microns and the slit has a width of 3.0 to 5.0 microns, the drainage grooves are in communication with the slits and extend to the connection via-hole, a length of a part of the drainage groove within the connection via-hole is 0.8 to 1.2 microns, and the drainage groove and the communicated slit have a same width and extension direction.

An array substrate, comprising:

• a base substrate;
• a drive circuit layer, disposed on one side of the base substrate and comprising a switching transistor;
• an insulating material layer, disposed on one side of the drive circuit layer distal to the base substrate, and having a connection via-hole exposing at least a part region of a drain electrode of the switching transistor;
• and
• an electrode layer, disposed on one side of the insulating material layer distal to the base substrate, wherein a surface of the electrode layer distal to the base substrate has at least one groove structure extending to the connection via-hole;
• wherein the electrode layer comprises a second electrode layer;
• and
• an opening of the connection via-hole is in a rectangular shape, a size of the opening of the connection via-hole close to the base substrate in an extension direction of a scan line in the drive circuit layer is 11.5˜13.5 microns, the size of the opening of the connection via-hole close to the base substrate in an extension direction of a data line in the drive circuit layer is 10 to 12 microns, and the size of the connection via-hole in the extension direction of the scan line is greater than the size of the connection via-hole in the extension direction of the data line, and
• the second electrode layer has a pixel electrode and covers the connection via-hole, the second electrode layer comprises a plurality of strip sub-electrodes, slits located among the strip sub-electrodes, and drainage grooves serving as the groove structures, wherein the strip sub-electrode has a width of 2.5 to 3.5 microns and the slit has a width of 3.0 to 5.0 microns, the drainage grooves are in communication with the slits and extend to the connection via-hole, a length of a part of the drainage groove within the connection via-hole is 1.5 to 2.5 microns, and the drainage groove and the communicated slit have a same width and extension direction.