Fin field-effect transistor device with composite liner for the fin
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWan-Yi Kao, Chung-Chi Ko
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Abstract
A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.
Claims20
A semiconductor device comprising:
- a fin protruding above a substrate;
- isolation regions on opposing sides of the fin;
- a gate structure over the fin;
- and
- a composite liner under the gate structure, comprising:
- a first layer, wherein the first layer is a first semiconductor material, wherein the first layer directly contacts and extends continuously along a first sidewall of the fin, along an upper surface of the fin distal from the substrate, and along a second sidewall of the fin opposing the first sidewall of the fin, wherein the first layer along the upper surface of the fin and the first layer along the first sidewall of the fin have a same composition, wherein a first portion of the first layer extends above an upper surface of the isolation regions distal from the substrate, wherein a second portion of the first layer extends below the upper surface of the isolation regions;
- and
- a second layer, wherein the second layer is a dielectric material, wherein the second layer contacts and extends along the second portion of the first layer, wherein the second layer is disposed between the first layer and the isolation regions.
A semiconductor device comprising:
- a fin protruding above a substrate;
- isolation regions on opposing sides of the fin;
- a composite liner along exterior surfaces of the fin, comprising:
- an interior layer directly contacting and extending along sidewalls of the fin and along an upper surface of the fin distal from the substrate, wherein the fin is crystalline silicon or crystalline silicon germanium, and the interior layer is amorphous silicon, wherein the interior layer along the upper surface of the fin and the interior layer along the sidewalls of the fin have a same composition;
- and
- an exterior layer over the interior layer and below an upper surface of the isolation regions distal from the substrate, wherein the exterior layer is disposed between the interior layer and the isolation regions, wherein the exterior layer is a first dielectric material;
- a gate dielectric layer over the upper surface of the isolation regions, wherein the gate dielectric layer contacts and extends along the interior layer of the composite liner;
- and
- a gate electrode over the gate dielectric layer.
A semiconductor device comprising:
- a fin protruding above a substrate;
- isolation regions on opposing sides of the fin;
- a composite liner along sidewalls of the fin and along an upper surface of the fin distal from the substrate, comprising:
- an interior layer around and directly contacting a channel region in the fin, the interior layer comprising a first semiconductor material, wherein the interior layer extends continuously along the upper surface of the fin from a first sidewall of the fin to a second opposing sidewall of the fin, wherein the interior layer along the upper surface of the fin and the interior layer along the first sidewall of the fin have a same composition;
- and
- an exterior layer on the interior layer, the exterior layer comprising a first dielectric material, wherein the exterior layer of the composite liner is disposed between the interior layer and the isolation regions;
- a gate dielectric layer on the interior layer, wherein the gate dielectric layer contacts and extends along the interior layer of the composite liner;
- and
- a gate electrode over the gate dielectric layer.
Dependencies are inferred from the claim text.