Fabrication of field effect transistors with ferroelectric materials

A semiconductor structure, comprising:

• a semiconductor fin disposed over a substrate;
• an isolation structure disposed over the substrate and surrounding the semiconductor fin;
• a metal gate structure disposed over the semiconductor fin, wherein the metal gate structure includes an interfacial layer, a hafnium oxide layer disposed over the interfacial layer, and a metal gate electrode disposed over the hafnium oxide layer, wherein the hafnium oxide layer is of a same and uniform material in its entirety;
• a gate spacer disposed along a sidewall of the metal gate structure, wherein a first portion of the hafnium oxide layer disposed along the gate spacer and interfacing side surfaces of the metal gate structure is thinner than a second portion of the hafnium oxide layer disposed directly over the interfacial layer, and a bottom surface of the first portion of the hafnium oxide layer is below a bottom surface of the second portion of the hafnium oxide layer;
• a source/drain feature disposed over the semiconductor fin and adjacent the gate spacer;
• and
• an interlayer dielectric (ILD) layer disposed over the source/drain feature and the isolation structure, wherein a bottom surface of the ILD layer is below a bottom surface of the source/drain feature,
• wherein electric dipoles within both the first and second portions of the hafnium oxide layer are oriented substantially in a same direction unidirectional and perpendicular to a top surface of the substrate.

A semiconductor structure, comprising:

• a semiconductor fin disposed over a substrate;
• a shallow trench isolation (STI) layer disposed over the substrate and surrounding the semiconductor fin;
• a metal gate structure disposed over the semiconductor fin, wherein the metal gate structure includes:
• an interfacial layer;
• a hafnium oxide layer disposed over the interfacial layer, wherein the hafnium oxide layer is of a same and uniform material in its entirety;
• and
• a metal gate electrode disposed over hafnium oxide layer;
• and
• a gate spacer disposed along a sidewall of the metal gate structure, wherein a first portion of the hafnium oxide layer disposed along the gate spacer and interfacing side surfaces of the metal gate structure has a first thickness and a second portion of the hafnium oxide layer disposed along the interfacial layer has a second thickness that is greater than the first thickness;
• a source/drain epitaxial feature disposed over the semiconductor fin and adjacent the metal gate structure;
• and
• an interlayer dielectric (ILD) layer disposed over the source/drain epitaxial feature and the STI layer, wherein the source/drain epitaxial feature is isolated from the STI layer by the ILD layer,
• wherein a top surface of the semiconductor fin is in direct contact with the interfacial layer, the second portion of the hafnium oxide layer, and the gate spacer,
• wherein both the first and second portions of the hafnium oxide layer are ferroelectric having a crystalline structure, wherein electric dipoles within both the first and second portions of the hafnium oxide layer are oriented substantially in a same direction parallel to each of a first applied electric field when forming the second portion of the hafnium oxide layer, a second applied electric field when forming the first portion of the hafnium oxide layer, and a third applied electric field when annealing the first and second portions of the hafnium oxide layer.