Tearing security feature of printed circuit substrates

Abstract

A structure of a circuitry substrate for securing an area from tampering is disclosed. The structure includes a circuitry substrate with at least one of a top tamper enclosure and a bottom tamper enclosure covering a component in a protected area of the circuitry substrate. The top and bottom tamper enclosures are adhesively bonded to a surface of the circuitry substrate, and a tear initiation site is added to a side of the perimeter of circuitry substrate bordering the protected area that includes at least one tamper enclosure, such that the tear initiation site is located and configured to enable propagation of a delamination of at least one internal layer of the circuitry substrate and a severing of a security circuit when a removal force is applied to the at least one of the top tamper enclosure and the bottom tamper enclosure.

Dependencies are inferred from the claim text.