Decision feedback equalizer with feedforward finite impulse response filter
AssigneeSynopsys, Inc.
InventorsRicardo Rodrigues, Rúben Sousa
Life of this patent
Estimating the term…
Abstract
An equalizer circuit includes: an analog front end circuit configured to receive an analog input signal from a transmission line; an analog finite impulse response filter circuit including: a sample and hold circuit configured to sample an output of the analog front end circuit; and a weighting circuit configured to weight the output of the analog front end circuit to generate a feedforward signal; and a decision feedback equalizer circuit configured to receive an output of the analog front end circuit and the feedforward signal.
Claims20
An equalizer circuit comprising:
- an analog front end circuit configured to receive an analog input signal from a transmission line;
- an analog finite impulse response filter circuit comprising:
- a sample and hold circuit configured to sample an output of the analog front end circuit;
- and
- a weighting circuit configured to weight the output of the analog front end circuit to generate a feedforward signal;
- a decision feedback equalizer circuit configured to receive an output of the analog front end circuit and the feedforward signal;
- and
- a first input port for receiving a coefficient for a first tap, the weighting circuit of the analog finite impulse response filter circuit being configured to weight the output of the analog front end circuit based on the coefficient for the first tap.
A receiver circuit comprising:
- an equalizer circuit comprising:
- an analog front end circuit configured to receive an analog input signal from a transmission line;
- an analog finite impulse response filter circuit comprising:
- a sample and hold circuit configured to sample an output of the analog front end circuit;
- and
- a weighting circuit configured to weight the output of the analog front end circuit to generate a feedforward signal;
- and
- a decision feedback equalizer circuit configured to receive an output of the analog front end circuit and the feedforward signal;
- a symbol decoder circuit configured to decode a stream of symbols received from the decision feedback equalizer circuit to generate a corresponding bitstream;
- and
- a controller configured to control the weighting circuit of the analog finite impulse response filter circuit to weight the output of the analog front end circuit based on a coefficient for a first tap.
A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to generate a digital representation of an integrated circuit comprising:
- an analog front end circuit configured to receive an analog input signal from a transmission line;
- an analog finite impulse response filter circuit comprising:
- a sample and hold circuit configured to sample an output of the analog front end circuit;
- and
- a weighting circuit configured to weight the output of the analog front end circuit to generate a feedforward signal;
- a decision feedback equalizer circuit configured to receive an output of the analog front end circuit and the feedforward signal;
- and
- a first input port for receiving a coefficient for a first tap, the weighting circuit of the analog finite impulse response filter circuit being configured to weight the output of the analog front end circuit based on the coefficient for the first tap.
Dependencies are inferred from the claim text.