Low-power multi-variable feedback control loop
AssigneeSynopsys, Inc.
InventorDavid Edgar Castle
Life of this patent
Estimating the term…
Abstract
A system includes a receiver that receives first data of a first data format at an input frequency. The system includes a transmitter that transmits second data of a second data format at a transmission frequency. The system includes a format converter, coupled between the receiver and the transmitter, that converts the first data to the second data. The format converter includes a phase-locked loop that provides an initial output frequency which is a product of a reference clock frequency and a first frequency multiplier. The format converter includes a feedback control loop that converts, using a one-bit floating-point converter, the initial output frequency of the phase-locked loop to a modified output frequency corresponding to the transmission frequency.
Claims11
A system comprising:
- a receiver configured to receive first data of a first data format at an input frequency;
- a transmitter configured to transmit second data of a second data format at a transmission frequency;
- and
- a format converter, coupled between the receiver and the transmitter, to convert the first data to the second data, wherein the format converter includes:
- a phase-locked loop (PLL) that provides an output frequency based on a first frequency multiplier value;
- and
- a control loop coupled to the PLL, wherein the control loop converts, using at least one of one-bit floating-point converters, the output frequency of the PLL to the transmission frequency,
- wherein the transmission frequency is based on a second frequency multiplier value of the control loop, and
- wherein the at least one of the one-bit floating-point converters generates a one-bit floating-point number from an integer value of the first data to convert the first frequency multiplier value into the second frequency multiplier value.
A device comprising:
- a period term calculation circuit, wherein the period term calculation circuit includes:
- a first one-bit floating-point converter configured to receive a first error value;
- a second one-bit floating-point converter configured to receive a target value;
- a first one-bit floating-point divider coupled to the first one-bit floating-point converter and the second one-bit floating-point converter;
- and
- a first one-bit floating-point multiplier configured to receive an input value and an output value of the first one-bit floating-point divider;
- and
- an adder-subtractor coupled to the first one-bit floating-point multiplier and configured to receive the input value, a first error sign value, and an output value of the first one-bit floating-point multiplier;
- to generate a first output value.
Dependencies are inferred from the claim text.