Reconfigurable analog-to-digital converter
AssigneeGoogle Inc.
InventorsKannan Aryaperumal Sankaragomathi, Johan Peter Vanderhaegen
Life of this patent
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Abstract
This disclosure describes apparatuses, methods, and techniques that enable a computing device to support a dynamic range of audio quality, varying bandwidths, varying sampling rates, numerous effective number of bits (ENOBs) resolutions, conserve power during an overall usage of the computing device, and enhance a user experience. To do so, the computing device utilizes a reconfigurable analog-to-digital converter (ADC). The reconfigurable ADC includes a successive-approximation-register (SAR) ADC, a noise-canceling circuit, and a noise-shaping circuit. The reconfigurable ADC can selectively operate in different modes of operation, in part, by enabling or disabling the noise-canceling circuit and the noise-shaping circuit.
Claims20
An apparatus comprising:
- a reconfigurable analog-to-digital converter (ADC), the reconfigurable ADC configured to selectively support at least two different resolution settings, the reconfigurable ADC including:
- a successive-approximation-register (SAR) ADC, the SAR ADC configured to:
- perform a first cycle of an N-bit analog-to-digital conversion of an analog input voltage to generate an N-bit digital output, the N-bit analog-to-digital conversion including a conversion noise and a residual voltage after the first cycle of the N-bit analog-to-digital conversion;
- and
- amplify a difference in the analog input voltage between two close time intervals;
- a noise-canceling circuit configured to lower the conversion noise by sampling the analog input voltage after amplifying the difference in the analog input voltage;
- and
- a noise-shaping circuit configured to add or subtract the residual voltage from the first cycle to a second cycle of the N-bit analog-to-digital conversion to reduce a quantization noise of the second cycle of the N-bit analog-to-digital conversion, the reconfigurable ADC being configured to selectively operate in one of at least two different modes of operation that comprise at least two of:
- a first mode of operation, the first mode of operation configured to use the SAR ADC, the noise-canceling circuit, and the noise-shaping circuit;
- a second mode of operation, the second mode of operation configured to use the SAR ADC and the noise-canceling circuit;
- a third mode of operation, the third mode of operation configured to use the SAR ADC and the noise-canceling circuit;
- and
- a fourth mode of operation, the fourth mode of operation configured to use the SAR ADC.
A method comprising:
- performing a first cycle of an N-bit analog-to-digital conversion of an analog input voltage by utilizing a successive-approximation-register (SAR) analog-to-digital converter (ADC) of a reconfigurable ADC;
- responsive to the performing, generating an N-bit digital output, and the N-bit analog-to-digital conversion including a conversion noise and a residual voltage;
- amplifying a difference in the analog input voltage between two close time intervals by utilizing a preamplifier with a gain A;
- sampling, after amplifying the difference in the analog input voltage between two close time intervals, the analog input voltage, by utilizing a noise-canceling circuit of the reconfigurable ADC;
- responsive to the sampling after the amplifying, lowering the conversion noise, the conversion noise being inversely related to a mathematical squaring of the gain A;
- responsive to the lowering of the conversion noise, increasing a first resolution of the first cycle of the N-bit analog-to-digital conversion;
- adding or subtracting the residual voltage from the first cycle to a second cycle of the N-bit analog-to-digital conversion by utilizing a noise-shaping circuit of the reconfigurable ADC;
- and
- responsive to the adding or subtracting, increasing a second resolution of the second cycle of the N-bit analog-to-digital conversion, the reconfigurable ADC selectively supporting at least two different resolution settings by operating in one of at least two different modes of operation that comprise at least two of:
- a first mode, the first mode utilizing the SAR ADC, the noise-canceling circuit, and the noise-shaping circuit;
- a second mode, the second mode utilizing the SAR ADC and the noise-canceling circuit;
- a third mode, the third mode utilizing the SAR ADC and the noise-canceling circuit;
- and
- a fourth mode, the fourth mode utilizing the SAR ADC.
Dependencies are inferred from the claim text.