Semiconductor structure, memory, and crack testing method
AssigneeChangxin Memory Technologies, Inc.
InventorShuangshuang Wu
Life of this patent
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Abstract
A semiconductor structure includes: a through silicon via penetrating a base; and a protection structure, including: a conductive first test ring and a conductive second test ring both arranged around the through silicon via and electrically insulated from the through silicon via; a first dielectric layer located between the first test ring and the second test ring and configured to electrically isolate the first test ring from the second test ring; and a first connection layer located in the first dielectric layer and configured to be electrically connected to the first test ring and the second test ring.
Claims14
A semiconductor structure, comprising:
- a through silicon via penetrating through a base;
- and
- a protection structure, comprising:
- a conductive first test ring and a conductive second test ring both arranged around the through silicon via and electrically insulated from the through silicon via;
- a first dielectric layer located between the first test ring and the second test ring and configured to electrically isolate the first test ring from the second test ring;
- and
- a first connection layer located in the first dielectric layer and configured to be electrically connected to the first test ring and the second test ring.
A memory, comprising:
- at least one semiconductor structure, wherein the semiconductor structure comprises a through silicon via penetrating through a base, and a protection structure, and wherein the protection structure comprises:
- a conductive first test ring and a conductive second test ring both arranged around the through silicon via and electrically insulated from the through silicon via;
- a first dielectric layer located between the first test ring and the second test ring and configured to electrically isolate the first test ring from the second test ring;
- and a first connection layer located in the first dielectric layer and configured to be electrically connected to the first test ring and the second test ring, and the base comprises a substrate and an insulating layer covering the substrate;
- and
- a storage element arranged in the insulating layer.
A crack testing method for testing a semiconductor structure, the semiconductor structure comprising a through silicon via penetrating through a base, and a protection structure, the protection structure comprising:
- a conductive first test ring and a conductive second test ring both arranged around the through silicon via and electrically insulated from the through silicon via;
- a first dielectric layer located between the first test ring and the second test ring and configured to electrically isolate the first test ring from the second test ring;
- and a first connection layer located in the first dielectric layer and configured to be electrically connected to the first test ring and the second test ring,
- the crack testing method comprising:
- providing the semiconductor structure;
- providing a first electrical signal to a first contact at an end of the first test ring and a second contact at an end of the second test ring, to determine a first electrical parameter of a first path arranged in the protection structure and electrically connected to the first contact and the second contact;
- in a case that the first electrical parameter satisfies a first preset condition, determining that no crack appears in the through silicon via;
- or
- in a case that the first electrical parameter does not satisfy a first preset condition, determining that cracks appear in the through silicon via.
Dependencies are inferred from the claim text.