Static random access memory with adaptive precharge signal generated in response to tracking operation
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., Tsmc Nanjing Company, Limited, Tsmc China Company Limited
InventorsXiu-Li Yang, He-Zhou Wan, Lu-Ping Kong, Wei-Yang Jiang
Life of this patent
Estimating the term…
Abstract
A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.
Claims20
A device, comprising:
- a memory array, comprising:
- a first tracking cell coupled to a tracking bit line and configured to generate a first tracking signal;
- a sense circuit configured to generate a first sense tracking signal in response to the first tracking signal;
- and
- a precharge circuit comprising:
- a first NAND gate configured to receive the first sense tracking signal;
- and
- a first invertor comprising an input coupled to an output of the first NAND gate,
- wherein the first invertor is configured to generate a precharge signal that rises in response to the first sense tracking signal rising.
A device, comprising:
- a first sense circuit configured to generate a first sense tracking signal in response to a first tracking signal that is associated with a plurality of first tracking cells;
- a second sense circuit configured to generate a second sense tracking signal in response to a second tracking signal that is associated with a plurality of second tracking cells;
- a precharge circuit, comprising:
- a first NAND gate configured to receive the first sense tracking signal;
- and
- a first invertor that comprises an input coupled to an output of the first NAND gate and configured to generate a precharge signal to precharge data lines;
- and
- a sense enable circuit, comprising:
- a second NAND gate configured to receive a delayed signal of the second sense tracking signal;
- and
- a second invertor that comprises an input coupled to an output of the second NAND gate and configured to generate a sense enable signal for enabling a sense amplifier circuit.
A method, comprising:
- turning on a plurality of transistors that are coupled to a first tracking bit line according to a clock signal to generate a first tracking signal;
- in response to the first tracking signal being at logic low, generating a first sense tracking signal that is at logic high;
- and
- in response to a read enable delayed signal from a latch circuit and the first sense tracking signal being at logic high, generating a precharge signal that is at logic high to precharge data lines.
Dependencies are inferred from the claim text.