Memory system with cached memory module operations
AssigneeRambus Inc.
InventorsFrederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
Life of this patent
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Abstract
A memory controller includes an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space. At least a portion of the DRAM storage space is configured as a cache for the SCM storage space. The interface to receive an incoming tag address for a read operation. Tag comparison circuitry performs a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache. The data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.
Claims20
A memory controller, comprising:
- an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space, at least a portion of the DRAM storage space configured as a cache for the SCM storage space, the interface to receive an incoming tag address for a read operation;
- tag comparison circuitry to perform a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache;
- and
- wherein the data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.
A method of operation in a memory controller, the method comprising:
- requesting an address for a read operation from dynamic random access memory (DRAM) storage space, at least a portion of the DRAM storage space configured as a DRAM cache for storage class memory (SCM) storage space;
- receiving the address as an incoming tag address from the DRAM storage space;
- performing a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache;
- and
- directly receiving, conditionally, first data from the addressed DRAM cache space based on the results of the comparison.
An integrated circuit (IC) chip, comprising:
- memory control circuitry, comprising:
- interface circuitry to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space, at least a portion of the DRAM storage space configured as a cache for the SCM storage space, the interface to receive an incoming address for a read operation;
- tag comparison circuitry to perform a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache;
- and
- wherein the data is received as read data directly from the addressed DRAM cache space when the comparison indicates a match between the incoming tag address and the stored tag addresses;
- and
- wherein the data is received as read data from a subsequently accessed portion of the SCM storage space that corresponds to the tag address when the comparison indicates a mismatch between the incoming tag address from the DRAM cache and the stored tag addresses.
Dependencies are inferred from the claim text.