Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency

A device comprising:

• a plurality of stages including:
• a fetch stage including circuitry configured to fetch a first instruction;
• a decode stage coupled to the fetch stage and including circuitry configured to decode the first instruction;
• and
• an execution stage coupled to the decode stage and including circuitry configured to execute the first instruction;
• a latency reduction circuit included within the decode stage, the latency reduction circuit including circuitry configured to execute the first instruction;
• and
• a pipeline control circuit coupled to the latency reduction circuit and configured to:
• determine whether to execute the first instruction by the execution stage or by the latency reduction circuit of the decode stage, based on determining whether executing the first instruction by the execution stage would cause a delay in execution of a second instruction that depends on the first instruction;
• and
• based on determining to execute the first instruction by the latency reduction circuit, stall operations of the plurality of stages for a single pipeline cycle.

A method comprising:

• performing a first determination as to whether performing an execute operation on a first instruction using an execute stage delays a second instruction that depends on the first instruction;
• based on the first determination, performing a second determination as to whether to cause (a) the execute stage or (b) execute logic within a fetch stage or a decode stage to perform the execute operation on the first instruction;
• and
• based on the second determination, performing a third determination as to whether or not to stall the fetch stage, the decode stage, and the execute stage.