US 12,411,689 B2 · Method to reduce register access latency in split-die SoC designs

Abstract

Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets interconnected with a plurality of Embedded Multi-Die Interconnect Bridges (EMIBs). The dielets include core dielets having cores, cache controllers and memory controllers. The method provides an affinity between a control and status registers (CSRs) memory range for the NL sockets such that CSRs in the memory controllers for multiple core dielets are programmed using transactions forwarded along core-to-cache controller datapaths that avoid crossing EMIBs. In one aspect, a transient map of address ranges is created that includes a respective Sub-NUMA Cluster (SNC) range allocated for the NL sockets, with a range of CSR addresses for accessing CSRs in the memory controllers for the NL sockets being stored in the respective SNC ranges.

Claims20

Dependent claims

A method implemented on a multi-socket platform comprising a plurality of sockets including a legacy socket and one or more non-legacy sockets, each of the legacy and non-legacy sockets comprising a split-die System-on-Chip (SoC) including a plurality of dielets interconnected with a plurality of embedded interconnect bridges connecting multiple dies, wherein the plurality of dielets include at least two core dielets having a plurality of cores, a plurality of cache controllers, and one or more memory controllers coupled to system memory, the method comprising:

accessing, on a non-legacy socket, control and status registers (CSRs) residing in the one or more memory controllers on the at least two core dielets using a plurality of transactions originating from a first core on a first core dielet of the at least two core dielets, wherein the plurality of transactions are forwarded via core-to-cache controller datapaths that do not cross an embedded interconnect bridges connecting multiple dies.

A multi-socket compute platform comprising:

system memory, comprising a plurality of memory devices;
and
a plurality of sockets including a legacy socket and one or more non-legacy sockets, each socket comprising,
a split-die System-on-Chip (SoC) including a plurality of dielets interconnected with a plurality of embedded interconnect bridges connecting multiple dies, wherein the plurality of dielets include at least two core dielets having a plurality of cores, a plurality of cache controllers, and one or more memory controllers, each memory controller coupled to at least one of the plurality of memory devices;
and
system firmware configured to be executed on one or more cores in the legacy socket and a non-legacy socket to access control and status registers (CSRs) residing in the one or more memory controllers on the at least two core dielets on the non-legacy socket using a plurality of transactions originating from a first core on a first core dielet of the at least two core dielets, wherein the plurality of transactions are not forwarded along any core-to-cache controller datapaths that cross an embedded interconnect bridges connecting multiple dies.

3 more elements

A non-transitory machine-readable medium having firmware instructions stored therein configured to be executed on one or more cores in a legacy socket and a non-legacy socket in a multi-socket platform comprising a plurality of sockets including the legacy socket and one or more non-legacy sockets, each of the legacy and non-legacy sockets comprising a split-die System-on-Chip (SoC) including a plurality of dielets interconnected with a plurality of embedded interconnect bridges connecting multiple dies, wherein the plurality of dielets include at least two core dielets having a plurality of cores, a plurality of cache controllers, and one or more memory controllers coupled to system memory, wherein execution of the instructions access control and status registers (CSRs) residing in the memory controllers on the non-legacy socket using a plurality of transactions originating from a first core on a first core dielet of the at least two core dielets in the non-legacy socket, and wherein the plurality of transactions are not forwarded along any core-to-cache controller datapaths that cross an embedded interconnect bridges connecting multiple dies.

Dependencies are inferred from the claim text.

Method to reduce register access latency in split-die SoC designs

Life of this patent

Method to reduce register access latency in split-die SoC designs

Life of this patent

Abstract

Claims20