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US 12,411,169 B2Granted
System on chip including a PVT sensor and corresponding PVT sensing method
AssigneeSTMicroelectronics S.r.l.
InventorsRiccardo Condorelli, Antonino Mondello, Michele Alessandro Carrano
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Abstract
A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.
Claims34
A system-on-chip, comprising:
- a process-voltage-temperature (PVT) sensor, comprising:
- a filter circuit configured to receive an input patterned digital signal, propagate the input patterned digital signal in a manner responsive to process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip, and generate an output patterned digital signal;
- wherein the filter circuit comprises:
- a first delay circuit configured to delay the input patterned digital signal with a first delay dependent on said process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip;
- a first flip-flop circuit cadenced by a clock signal and having an input configured to receive a first delayed input patterned digital signal output from the first delay circuit;
- a second delay circuit configured to delay the input patterned digital signal with a second delay dependent on said process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip;
- a third delay circuit configured to delay the clock signal with a third delay to generate a delayed clock signal;
- and
- a second flip-flop circuit cadenced by the delayed clock signal and having an input configured to receive a second delayed input patterned digital signal output from the second delay circuit;
- and
- a digital comparison circuit configured to compare the input patterned digital signal and a first output patterned digital signal generated at an output of the first flip-flop circuit and generate a first warning signal when the comparison finds signal discrepancies between the input patterned digital signal and the first output patterned digital signal and compare the input patterned digital signal and a second output patterned digital signal generated at an output of the second flip-flop circuit and generate a second warning signal when the comparison finds signal discrepancies between the input patterned digital signal and the second output patterned digital signal.
8 more elements
A system-on-chip, comprising:
- a process-voltage-temperature (PVT) sensor, comprising:
- a filter circuit configured to receive an input patterned digital signal, propagate the input patterned digital signal in a manner responsive to process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip, and generate an output patterned digital signal;
- wherein the filter circuit comprises:
- a first flip-flop circuit cadenced by a clock signal and configured to propagate the input patterned digital signal as a first output patterned digital signal;
- a first delay circuit configured to delay the first output patterned digital signal with a first delay dependent on said process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip;
- a second delay circuit configured to delay the clock signal with a second delay to generate a delayed clock signal;
- and
- a second flip-flop circuit cadenced by the delayed clock signal and having an input configured to receive a further input patterned digital signal output from the first delay circuit;
- and
- a digital comparison circuit configured to compare the input patterned digital signal and the first output patterned digital signal and generate a first warning signal when the comparison finds signal discrepancies between the input patterned digital signal and the first output patterned digital signal and compare the further input patterned digital signal and a second output patterned digital signal generated at an output of the second flip-flop circuit and generate a second warning signal when the comparison finds signal discrepancies between the further input patterned digital signal and the second output patterned digital signal.
7 more elements
A method for sensing process-voltage-temperature (PVT) variations in a system-on-chip, comprising:
- generating an input patterned digital signal;
- propagating the input patterned digital signal by a filter circuit in a manner responsive to process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip to generate an output patterned digital signal;
- wherein propagating the input patterned digital signal comprises:
- applying a first delay on the input patterned digital signal wherein the first delay is dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip;
- passing a first delayed patterned digital signal output from the first delay through a first flip-flop circuit cadenced by a clock signal;
- applying a second delay on the input patterned digital signal wherein the second delay is dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip;
- applying a third delay on the clock signal to generate a delayed clock signal;
- and
- passing a second delayed patterned digital signal output from the second delay through a second flip-flop circuit cadenced by the delayed clock signal;
- digitally comparing the input patterned digital signal and a first output patterned digital signal generated by the first flip-flop circuit;
- generating a first warning signal in response to detection of discrepancies between the input patterned digital signal and the first output patterned digital signal;
- digitally comparing the input patterned digital signal and a second output patterned digital signal generated by the second flip-flop circuit;
- and
- generating a second warning signal in response to detection of discrepancies between the input patterned digital signal and the second output patterned digital signal.
11 more elements
A method for sensing process-voltage-temperature (PVT) variations in a system-on-chip, comprising:
- generating an input patterned digital signal;
- propagating the input patterned digital signal by a filter circuit in a manner responsive to process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip to generate an output patterned digital signal;
- wherein propagating the input patterned digital signal comprises:
- passing the input patterned digital signal through a first flip-flop circuit cadenced by a clock signal to generate a first output patterned digital signal;
- and
- applying a first delay on the first output patterned digital signal to generate a further input patterned data signal;
- applying a second delay on the clock signal to generate a delayed clock signal;
- passing the further input patterned data signal through a second flip-flop circuit cadenced by the delayed clock signal;
- wherein the first delay and second delay are dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip;
- digitally comparing the input patterned digital signal and the first output patterned digital signal generated by the first flip-flop circuit;
- generating a first warning signal in response to detection of discrepancies between the input patterned digital signal and the first output patterned digital signal;
- digitally comparing the further input patterned digital signal and a second output patterned digital signal generated by the second flip-flop circuit;
- and
- generating a second warning signal in response to detection of discrepancies between the further input patterned digital signal and the second output patterned digital signal.
11 more elements
Dependencies are inferred from the claim text.