Superconducting anti-fuse based field programmable gate array

A superconducting anti-fuse based field programmable gate array (FPGA), comprising:

• a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer arranged sequentially in a direction away from a semiconductor layer, wherein the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are different from one another;
• wherein the fourth metal layer includes a set of active superconducting components;
• wherein the second metal layer includes a first set of superconducting passive transmission lines (PTLs), wherein a first superconducting passive transmission line (PTL) in the first set of superconducting PTLs connects a first PTL driver with a first PTL receiver which are disposed on the fourth metal layer, wherein the first PTL driver drives the first superconducting PTL with a non-single-flux-quantum-pulse, and wherein the first PTL receiver converts the non-single-flux-quantum pulse received over the first superconducting PTL into a single-flux-quantum pulse;
• wherein the third metal layer includes a second set of superconducting PTLs, wherein a second superconducting PTL in the second set of superconducting PTLs connects a second PTL driver with a second PTL receiver which are disposed on the fourth metal layer;
• at least one anti-fuse located at an intersection of a third superconducting PTL from the first set of superconducting PTLs and a fourth superconducting PTL from the second set of superconducting PTLs, wherein the at least one anti-fuse is located between the second metal layer and the third metal layer, wherein a first terminal of the anti-fuse is electrically connected to the third superconducting PTL and a second terminal of the anti-fuse is electrically connected to the fourth superconducting PTL, wherein the anti-fuse has a first state which is an unprogrammed state and a second state which is a programmed state, wherein the anti-fuse has a non-zero resistance above and below a critical temperature in the first state, wherein the anti-fuse has a non-zero resistance above the critical temperature and a zero resistance below the critical temperature in the second state, wherein the anti-fuse comprises two superconducting structures separated by a dielectric material, and wherein the dielectric material is insulating in the first state and superconducting in the second state;
• wherein the semiconductor layer includes a complementary metal-oxide-semiconductor (CMOS) circuit to transition the anti-fuse from the first state to the second state;
• and
• wherein the first metal layer provides connectivity between devices in the CMOS circuit.

An apparatus, comprising:

• a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer arranged sequentially in a direction away from a semiconductor layer, wherein the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are different from one another;
• wherein the second metal layer includes a first set of superconducting passive transmission lines (PTLs), wherein a first superconducting passive transmission line (PTL) in the first set of superconducting PTLs connects a first PTL driver with a first PTL receiver which are disposed on the fourth metal layer, wherein the first PTL driver drives the first superconducting PTL with a non-single-flux-quantum-pulse, and wherein the first PTL receiver converts the non-single-flux-quantum pulse received over the first superconducting PTL into a single-flux-quantum pulse;
• wherein the third metal layer includes a second set of superconducting PTLs, wherein a second superconducting PTL in the second set of superconducting PTLs connects a second PTL driver with a second PTL receiver which are disposed on the fourth metal layer;
• at least one anti-fuse located at an intersection of a third superconducting PTL from the first set of superconducting PTLs and a fourth superconducting PTL from the second set of superconducting PTLs, wherein the at least one anti-fuse is located between the second metal layer and the third metal layer, wherein a first terminal of the anti-fuse is electrically connected to the third superconducting PTL and a second terminal of the anti-fuse is electrically connected to the fourth superconducting PTL, wherein the anti-fuse has a first state which is an unprogrammed state and a second state which is a programmed state, wherein the anti-fuse has a non-zero resistance above and below a critical temperature in the first state, wherein the anti-fuse has a non-zero resistance above the critical temperature and a zero resistance below the critical temperature in the second state, wherein the anti-fuse comprises two superconducting structures separated by a dielectric material, and wherein the dielectric material is insulating in the first state and superconducting in the second state;
• wherein the fourth metal layer includes a set of active superconducting components arranged in rows;
• wherein the semiconductor layer includes a memory circuit;
• wherein the semiconductor layer includes a complementary metal-oxide-semiconductor (CMOS) circuit to transition the antifuse from the first state to the second state;
• and
• wherein the first metal layer provides connectivity between devices in the CMOS circuit.