Digital-to-analog converter and a method for reducing aging effects on components of the digital-to-analog converter
AssigneeIntel Corporation
InventorsDaniel Gruber, Michael Kalcher, Alessandra Cangianiello
Life of this patent
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Abstract
A digital-to-analog converter (DAC). A DAC includes a plurality of DAC cells and a controller. The controller generates a control signal for driving the plurality of DAC cells for each clock cycle. The controller may generate the control signal to select a set of one or more DAC cells for an input code or for a standby mode of the DAC such that the selected set of one or more DAC cells to be active for the same input code or for the standby mode of the DAC change over time without affecting an output of the DAC more than a predetermined limit.
Claims19
A digital-to-analog converter (DAC) comprising:
- a plurality of DAC cells;
- and
- a controller configured to generate a control signal to drive the plurality of DAC cells for each clock cycle, wherein the controller is configured to generate the control signal to select a set of at least one DAC cell for an input code or for a standby mode of the DAC such that the selected set of at least one DAC cell to be active for the same input code or for the standby mode of the DAC change during a predetermined period of time, wherein an output of the DAC is less than or equal to a predefined threshold,
- wherein during a normal operation of the DAC where the DAC generates the output based on the input code, the controller is configured to generate the control signal in a way that one or more low-indexed DAC cells are swapped with one or more high-indexed DAC cells such that the selected set of at least one DAC cell to be active for the same input code changes during the predetermined period of time.
A method for reducing aging effects on components of a digital-to-analog converter (DAC), wherein the DAC comprises a plurality of DAC cells, the method comprising:
- generating a control signal for driving the plurality of DAC cells for each clock cycle, wherein the control signal is generated to select a set of at least one DAC cell for an input code or for a standby mode of the DAC such that the selected set of at least one DAC cell to be active for the same input code or for the standby mode of the DAC change during a predetermined period of time, wherein an output of the DAC is less than or equal to a predefined threshold;
- and
- sending the control signal to the DAC cells,
- wherein during a normal operation of the DAC where the DAC generates the output based on the input code, the control signal is generated in a way that one or more low-indexed DAC cells are swapped with one or more high-indexed DAC cells such that the selected set of at least one DAC cell to be active for the same input code changes during the predetermined period of time.
Dependencies are inferred from the claim text.