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US 12,406,971 B2Granted
Staggered dual-side multi-chip interconnect
AssigneeNVIDIA Corporation
InventorsShuo Zhang, Eric Zhu, Minto Zheng, Michael Zhai, Town Zhang, Jie Ma
Life of this patent
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Abstract
Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.
Claims23
A device comprising:
- a first circuit package mounted on a first side of a substrate;
- and
- a second circuit package mounted on a second side of the substrate in a stacked and staggered layout with the first circuit package;
- vias forming a direct vertical connection through the substrate between input/output (IO) pins of the first circuit package and IO pins of the second circuit package in a region of the substrate overlapped by the first circuit package and the second circuit package;
- and
- wherein the IO pins of the first circuit package are located exclusively in rows extending end-to-end along a single side of the first circuit package, and the IO pins of the second circuit package are located exclusively in rows extending end-to-end along a single side of the second circuit package.
3 more elements
A device comprising:
- a first circuit and a second circuit mounted on opposite sides of a substrate in a stacked and staggered layout;
- and
- wherein peripheral regions of the first circuit and the second circuit that together form the entirety of an overlapped interconnect region of the stacked and staggered layout comprise one of a uniform row pair configuration of pins in direct vertical alignment, an interleaved staggered row pair configuration of pins in direct vertical alignment, and an interleaved uniform row configuration of pins in direct vertical alignment.
A circuit board comprising:
- a first integrated circuit mounted on a first side of the circuit board;
- a second integrated circuit mounted on a second side of the circuit board in a stacked and staggered layout with the first integrated circuit;
- vertical vias configured in the circuit board in an overlapped interconnect region of the stacked and staggered layout, the vertical vias forming directly vertical connections between data transmitter pins of the first integrated circuit and data receiver pins of the second integrated circuit;
- and
- wherein the transmitter pins are located exclusively in rows extending end-to-end along a single side of the first integrated circuit, and the receiver pins are located exclusively in rows extending end-to-end along a single side of the second integrated circuit.
2 more elements
An electronic assembly comprising:
- a substrate comprising:
- a first side,
- a second side opposite the first side, and
- a plurality of vias extending directly vertically through the substrate from the first side to the second side;
- a first circuit package mounted on the first side of the substrate and including a first plurality of input/output (IO) connection points organized into rows extending end-to-end exclusively along a single side of the first circuit package;
- and
- a second circuit package mounted on the second side of the substrate in a stacked and staggered layout with the first circuit package and including a second plurality of IO connection points organized into rows extending end-to-end exclusively along a single side of the second circuit package;
- and
- the vias connecting the first plurality of IO connection points and the second plurality of IO connection points in an overlap region of the substrate overlapped by both the first circuit package and the second circuit package, the overlap region formed entirely by an area comprising the first plurality of IO connection points and the second plurality of IO connection points.
6 more elements
Dependencies are inferred from the claim text.