Rate enhanced pulsed DC sputtering system

A non-transitory memory including non-transitory instructions that are,

• at least one of, executable by a processor to execute a method and accessible by a field programmable gate array to configure the field programmable gate array to execute the method, the method comprising:
• causing a first power source to apply a first voltage to a first power lead that alternates between positive and negative relative to a second power lead;
• causing a second power source to apply a second voltage to a third power lead that alternates between positive and negative relative to the second power lead;
• and
• causing the first power source and the second power source to phase-synchronize the first voltage with the second voltage, so both, the first voltage and the second voltage simultaneously cross zero volts.

A method of pulsed direct current sputtering, comprising:

• providing a first power lead, a second power lead, and a third power lead;
• coupling a first power source to the first power lead and the second power lead;
• coupling a second power source to the third power lead and the second power lead;
• coupling a controller to both the first and second power sources;
• applying, with the first power source, a first voltage to the first power lead that alternates between positive and negative relative to the first-second power lead;
• applying, with the second power source, a second voltage to the third power lead that alternates between positive and negative relative to the second power lead;
• and
• phase-synchronizing, with the controller, the first voltage with the second voltage, so both, the first voltage and the second voltage, are simultaneously cross zero volts.