Storage and accessing methods for parameters in streaming AI accelerator chip

A streaming-based data buffer comprising:

• a plurality of banks, different banks being configured to store different data;
• a data read circuit configured to receive a read control signal and a read address corresponding to a computation task, in the case the read control signal corresponds to a first read mode, determine n banks from the plurality of banks based on the read control signal, and read a first data required for performing the computation task in parallel from the n banks based on the read address, the first data comprising n pieces of data corresponding to the n banks in a one-to-one correspondence, n≥2, n being a positive integer;
• wherein the read address comprises an addressing address and a chip select address, the data read circuit is configured to read the first data based on the addressing address;
• the data read circuit is further configured to, in the case the read control signal corresponds to a second read mode, determine one bank from the plurality of banks based on the chip select address and read a second data required for performing the computation task from the one bank based on the addressing address;
• and
• the read control signal corresponds to the second read mode in the case the computation task is a bilinear interpolation in the neural network algorithm.