Semiconductor memory device performing target refresh and memory system including the same
AssigneeSK hynix Inc.
InventorWoongrae Kim
Life of this patent
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Abstract
A memory system includes: a memory controller suitable for generating a first target address by sampling an address according to an active command, and providing the active command, a precharge command, a normal refresh command, the address and the first target address, to a memory device; and the memory device suitable for generating a first target refresh command according to the precharge command and the address, and refreshing one or more word lines corresponding to the first target address according to the first target refresh command.
Claims24
A memory system, comprising:
- a memory device for storing data;
- a memory controller outside the memory device and suitable for generating a first target address, wherein the memory controller samples an address according to an active command, and provides the active command, a precharge command, a normal refresh command, the address and the first target address, to the memory device;
- and
- the memory device suitable for generating a first target refresh command, wherein the first target refresh command is generated according to the precharge command provided from the memory controller outside the memory device and the address provided from the memory controller outside the memory device, and one or more word lines corresponding to the first target address is refreshed according to the first target refresh command.
A semiconductor memory device, comprising:
- a refresh command control circuit suitable for:
- generating a first target refresh command according to a mode entry signal that is generated by an address and a precharge command,
- generating a second target refresh command according to a normal refresh command, and
- generating a final target refresh command according to the first target refresh command or the second target refresh command;
- an active latch suitable for latching the address as an active address according to an active command;
- a refresh address control circuit suitable for:
- generating a first target address by latching the active address according to the mode entry signal,
- generating a second target address by randomly sampling the active address, and
- providing a row-hammer address by selecting one of the first target address and the second target address;
- and
- a row control circuit suitable for refreshing one or more word lines corresponding to the row-hammer address according to the final target refresh command.
A semiconductor memory device, comprising:
- a refresh command control circuit suitable for generating a target refresh command according to a mode entry signal that is generated by an address and a precharge command;
- an active latch suitable for latching the address as an active address according to an active command;
- a refresh address control circuit suitable for generating a target address by latching the active address according to the mode entry signal;
- and
- a row control circuit suitable for refreshing one or more word lines corresponding to the target address according to the target refresh command.
An operating method of a memory device, comprising:
- latching an address as an active address according to an active command;
- generating a mode entry signal according to a specific bit of the address and a precharge command;
- generating a first target refresh command by delaying the mode entry signal by a scheduled time;
- generating a first target address by latching the active address according to the mode entry signal;
- and
- refreshing one or more word lines corresponding to the first target address according to the first target refresh command.
An operating method of a memory system, the operating method comprising:
- providing, by a controller outside a memory device for storing data, a set of an indicator and a precharge command;
- and
- performing, by the memory device, a target refresh operation according to an active address in response to at least one of the set provided by the controller outside the memory device and a predetermined number of inputs of a refresh command.
Dependencies are inferred from the claim text.