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US 12,406,704 B2Granted
Multi-stage bit line pre-charge
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Cheng Wu, Kao-Cheng Lin, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin, Wei Min Chan, Yen-Huei Chen
Life of this patent
Estimating the term…
Abstract
Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.
Claims20
A circuit comprising:
- a bit cell responsive to a bit line and a bit line bar;
- a pre-charge circuit including:
- a first pre-charge component configured to charge the bit line and the bit line bar prior to conclusion of a read operation;
- and
- a second pre-charge component configured to charge the bit line and the bit line bar at the end of the read operation, wherein:
- the first pre-charge component of the pre-charge circuit includes a first transistor and a second transistor;
- the first transistor has a gate terminal configured to receive a first control signal and a source/drain terminal connected to a first source/drain terminal of the second transistor;
- and
- the second transistor has a gate terminal and a second source/drain terminal connected to each other and to both the bit line and the bit line bar;
- and
- a pre-charge control circuit configured to provide the first control signal to the first pre-charge component and a second control signal to the second pre-charge component, wherein:
- the first control signal is transitioned from inhibiting charging to enable charging by the first pre-charging component prior to deactivation of a word line;
- and
- the second control signal is transitioned to from inhibiting charging to enable charging by the second pre-charge component after transitioning of the first control signal.
11 more elements
A method comprising:
- providing a first control signal to a first pre-charge component inhibiting charging of a bit line or a bit line bar;
- providing a second control signal to a second pre-charge component inhibiting charging of the bit line or the bit line bar, wherein the first pre-charge component includes a first transistor having a gate configured to receive the first control signal, a first source/drain terminal configured to receive the second control signal, and a second source/drain terminal connected to both the bit line and the bit line bar;
- and
- the second pre-charge component includes a third transistor and a fourth transistor having a first source/drain terminal connected to a source/drain terminal of the third transistor, a gate terminal connected to a gate terminal of the third transistor, and a second source/drain terminal connected to the bit line;
- transitioning the first control signal to enable charging of the bit line or the bit line bar prior to deactivation of a word line;
- and
- transitioning the second control signal to enable charging of the bit line or the bit line bar after the deactivation of the word line.
4 more elements
A memory comprising:
- an array of bit cells;
- a pre-charge circuit associated with the bit cells;
- and
- a pre-charge control circuit configured to provide a first control signal to a first pre-charge component of the pre-charge circuit and a second control signal to a second pre-charge component of the pre-charge circuit, wherein the first pre-charge component is configured to charge a bit line or a bit line bar prior to conclusion of a read operation and the second pre-charge component is configured to charge the bit line or the bit line bar at the end of the read operation,
- wherein the first pre-charge component includes a first transistor and a second transistor, the first transistor has a source/drain terminal connected to a first source/drain terminal of the second transistor, the second transistor has a gate terminal and a second source/drain terminal connected to each other and to both the bit line and the bit line bar, the first transistor has a gate terminal configured to receive the first control signal;
- wherein:
- the first control signal is provided to the first pre-charge component inhibiting charging during a portion of a read operation;
- a word line associated with a bit cell is activated during the read operation;
- the second control signal is provided to the second pre-charge component inhibiting charging during at least the portion of a read operation;
- the first control signal is transitioned to enable charging by the first pre-charge component prior to deactivation of the word line;
- and
- the second control signal is transitioned to enable charging by the second pre-charge component after transitioning the first control signal.
9 more elements
Dependencies are inferred from the claim text.