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US 12,406,121 B2Granted
3D integrated circuit with enhanced debugging capability
AssigneeXilinx, Inc.
InventorPongstorn Maidee
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.
Claims16
A method, comprising:
- testing a plurality of layers of a 3-dimensional integrated circuit (3D IC), wherein each layer is subdivided into a plurality of regions, wherein the regions from one layer to another are aligned within stacked columns;
- determining which regions of the plurality of layers are operational;
- determining a number of operational regions in each stacked column;
- and
- for each stacked column including a number of operational regions exceeding a number of operational regions reserved for user circuitry, designating a selected region of a selected layer of the plurality of layers as a debug region.
2 more elements
An integrated circuit, comprising:
- a plurality of layers, wherein each layer is subdivided into a plurality of regions such that the regions from one layer to another are aligned within stacked columns;
- wherein, based on testing of the plurality of layers, a number of regions of each layer of the plurality of layers within each stacked column are designated as operational;
- and
- wherein, for each stacked column including a number of operational regions exceeding a number of operational regions reserved for user circuitry, a selected region of a selected layer of the plurality of layers is designated as a debug region.
1 more element
Dependencies are inferred from the claim text.