Storage device for high speed link startup and storage system including the same

A host device comprising:

• an interconnect part comprising at least one receiver and at least one transmitter,
• wherein the interconnect part is configured to perform data communication through a transmission lane and a reception lane among at least one lane connected between the host device and a storage device,
• wherein the host device is configured to perform link startup in a high speed mode through the reception lane and the transmission lane when the at least one receiver determines whether to receive a high speed link up message from the storage device through the reception lane and receives the high speed link up message from the storage device as a result of the determination, wherein a line in the transmission lane transitions from a zero differential line voltage DIF-Z to an activate period having a negative differential line voltage DIF-N,
• wherein the host device is configured to be initialized to the high speed mode and then determine whether to receive the high speed link up message from the storage device through the reception lane in a stand-by state, and
• wherein, when a length of the activate period is less than a reference time, the transmission lane and the reception lane enter the high speed mode, and when the length of the activate period is equal to or greater than the reference time, the transmission lane and the reception lane enter a low speed mode.

A system comprising:

• a host device connected to a storage device through a plurality of lanes, the storage device including at least one receiver and at least one transmitter that are configured to perform data communication with the host device through a connected transmission lane and a connected reception lane among the plurality of lanes,
• wherein the storage device is further configured for the at least one transmitter to transmit a high speed link up message to the host device through the transmission lane such that a line in the transmission lane transitions from a zero differential line voltage DIF-Z to an activate period having a negative differential line voltage DIF-N, and configured to perform link startup in a high speed mode through the transmission lane and the reception lane based on the high speed link up message when a low speed link up message is not received from the host device through the reception lane within a set time from the transmission of the high speed link up message,
• wherein the storage device is configured to perform an initialization operation and then transmits the high speed link up message to the host device, and
• wherein, when a length of the activate period is less than a reference time, the transmission lane and the reception lane enter the high speed mode.