Integrated circuit device and method for fabricating the same
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
InventorsJenn-Gwo Hwu, Jian-Yu Lin
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Abstract
An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.
Claims20
A method for fabricating an integrated circuit device, comprising:
- etching at least one trench in a semiconductor substrate to form a protruding portion of the semiconductor substrate, wherein the protruding portion has a top surface and a sidewall extending downwards from the top surface of the protruding portion and surrounding the top surface of the protruding portion;
- forming an isolation structure surrounding the protruding portion of the semiconductor substrate;
- forming a doped semiconductor region in the semiconductor substrate, wherein the doped semiconductor region is directly below the protruding portion, and has a higher dopant concentration than the protruding portion of the semiconductor substrate;
- forming a tunneling layer over the top surface and the sidewall of the protruding portion;
- forming a top electrode over a first portion, of the tunneling layer over the top surface of the protruding portion, the top electrode vertically overlapping an entirety of the top surface of the protruding portion and a portion of the sidewall of the protruding portion adjoining the top surface of the protruding portion, wherein a second portion of the tunneling layer extends beyond a sidewall of the top electrode, and at least a part of the second portion of the tunneling layer has a top surface lower than a top surface of the first portion of the tunneling layer;
- and
- forming a contact extending through the isolation structure and electrically connected with the doped semiconductor region.
A method for fabricating an integrated circuit device, comprising:
- patterning a semiconductor substrate to form at least one protruding portion and at least one semiconductor fin;
- forming a tunneling layer over the at least one protruding portion;
- forming a gate dielectric layer over the at least one semiconductor fin;
- depositing an electrode layer over the tunneling layer and the gate dielectric layer;
- patterning the electrode layer into at least one top electrode over the tunneling layer and a gate electrode over the gate dielectric layer, wherein the tunneling layer extends beyond opposite sidewalls of the top electrode, and one of the sidewalls of the top electrode is vertically overlapping with a sidewall of the protruding portion;
- and
- forming an interlayer dielectric layer over the semiconductor substrate, wherein the interlayer dielectric layer is in contact with an interface between the tunneling layer and the gate dielectric layer.
A method for fabricating an integrated circuit device, comprising:
- forming a protruding portion over a semiconductor substrate;
- forming an isolation structure surrounding a bottom portion of the protruding portion, wherein a top portion of the protruding portion is higher than a top surface of the isolation structure;
- forming a tunneling layer over the isolation structure and surrounding the top portion of the protruding portion;
- depositing an electrode layer over the tunneling layer;
- and
- patterning the electrode layer into a top electrode over the protruding portion, wherein a sidewall of the top electrode is vertically overlapping with a sidewall of the protruding portion, a vertical portion of the tunneling layer surrounding the top portion of the protruding portion and a lateral portion of the tunneling layer extending along the isolation structure are exposed as a result of patterning the electrode layer into the top electrode, and the vertical portion of the tunneling layer is in contact with the sidewall of the protruding portion.
Dependencies are inferred from the claim text.