Clock and data recovery circuit and a display apparatus having the same

An operating method of a display driving integrated circuit, comprising:

• receiving a reference clock from a timing controller in an initial training mode;
• synchronizing phases of an internal clock and the reference clock in the initial training mode;
• receiving a data packet from the timing controller in a normal operating mode;
• recovering a data signal and clock signal synchronized with the data packet in the normal operating mode,
• wherein the synchronizing the phases includes:
• detecting a frequency band of the reference clock using the internal clock;
• and
• adjusting at least one parameter of a Clock and Data Recovery (CDR) circuit according to the frequency band.

An operating method of a display device, comprising:

• receiving a data packet at a display driving integrated circuit, wherein the data packet is provided from a timing controller;
• recovering a data signal and a clock signal synchronized with the data packet in a Clock and Data Recovery (CDR) circuit of the display driving integrated circuit;
• and
• displaying the data signal on a display panel,
• wherein the CDR circuit detects a frequency band of a reference clock using an initial clock, and adjusts at least one parameter of the CDR circuit according to the frequency band.