Dynamic timing loop gain to compensate phase interpolation nonlinearities

A clock recovery method that comprises, in an integrated receiver circuit:

• providing a phase control signal to a phase interpolator to derive a sampling signal from a clock signal;
• sampling an analog receive signal in accordance with the sampling signal to obtain a digital receive signal;
• producing a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal;
• and
• deriving the phase control signal from the estimated timing error, said deriving including scaling the estimated timing error by a scale factor that depends on the phase control signal.

A nontransient information storage medium having a semiconductor intellectual property core to generate circuitry comprising:

• a phase interpolator configured to provide a sampling signal by applying a phase shift to a clock signal in response to a phase control signal;
• a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with the sampling signal;
• a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal;
• and
• a feedback circuit configured to derive the phase control signal from the timing error signal, the feedback circuit including a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.