PLL circuit and transmission system
AssigneeNuvoton Technology Corporation Japan
InventorsMayuko Fujita, Akinori Shimmyo
Life of this patent
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Abstract
A phase-locked loop (PLL) circuit generates an output clock signal and includes: a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal.
Claims10
A phase-locked loop (PLL) circuit that generates an output clock signal, the PLL circuit comprising:
- a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit;
- and
- a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal,
- wherein the control circuit resets the frequency divider when the switch is made for the selection of the reference clock signal, and
- a period in which the division ratio is temporarily reduced is a single cycle or a plurality of cycles of the feedback clock signal immediately after reset cancel of the frequency divider.
A phase-locked loop (PLL) circuit that generates an output clock signal, the PLL circuit comprising:
- a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit;
- and
- a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal, wherein
- the control circuit temporarily changes the division ratio from N to (N-m) when the switch is made for the selection of the reference clock signal, where N is an integer indicating a division ratio in a locked state before the reference clock signal is switched, and m is an integer corresponding to a time difference between an edge timing of the reference clock signal immediately after the reference clock signal is switched and a start timing of the frequency divider immediately after reset cancel.
A phase-locked loop (PLL) circuit that generates an output clock signal, the PLL circuit comprising:
- a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit;
- and
- a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal, wherein
- the selection circuit has a stop period during which the selection circuit does not output the reference clock signal when the switch is made for the selection of the reference clock signal, and
- the control circuit brings the frequency divider into a reset state in the stop period and cancels the reset state of the frequency divider at an edge timing of the reference clock signal, the edge timing occurring when the stop period is ended.
Dependencies are inferred from the claim text.