Back to results
US 12,401,349 B2Granted
Single event upset hardened flip-flop and methods of operation
AssigneeNXP B.V.
InventorsRishabh Kaistha, Akhil Garg, Kunal Singh Sengar
Life of this patent
Estimating the term…
Abstract
A single event upset (SEU) hardened flip-flop comprises a master latch and a plurality of slave latches, where an output of the master latch is coupled to a respective input of the slave latches. A Muller element which has an input which is coupled to a respective output of the slave latches and an output which is coupled to a bus keeper. The bus keeper maintains a logic level output in presence of the SEU.
Claims19
A method comprising:
- receiving an input logic level at a master latch of a flip-flop at a first logic level transition of a clock, the master latch having only one latch;
- outputting by the master latch a logic level based on the input logic level;
- inputting the output logic level to a first slave latch and a second slave latch at a second logic level transition of the clock;
- and
- providing output logic levels of the first slave latch and second slave latch to a Muller element coupled to a bus keeper, wherein the Muller element outputs to the bus keeper a first logic level or second logic level when the output logic levels of the slave latches are the same and outputs a tri-state when the output logic levels of the slave latches are different which results from a single event upset (SEU), wherein a first logic level or second logic level output by the bus keeper does not change in presence of the SEU, wherein the bus keeper and Muller element are separated by a distance that both the bus keeper and Muller element are not impacted by the SEU and a duty cycle that the one master latch outputs the logic signal to the slave latches is selected to minimize effect of the SEU on the logic signal before being latched by the slave latches.
2 more elements
A single event upset (SEU) hardened flip-flop comprising:
- a master latch, the master latch having only one latch;
- a plurality of slave latches, wherein an output of the one master latch is coupled to a respective input of the slave latches;
- a Muller element, wherein an input of the Muller element is coupled to a respective output of the slave latches;
- and
- a bus keeper which is coupled to an output of the Muller element, wherein the bus keeper and Muller element are separated by a distance that both the bus keeper and Muller element are not impacted by the SEU and a duty cycle that the one master latch outputs the logic signal to the slave latches is selected to minimize effect of the SEU on the logic signal before being latched by the slave latches.
2 more elements
Dependencies are inferred from the claim text.