Electrical interconnects for packages containing photonic integrated circuits

A method for providing a system-in-package comprising a photonic integrated circuit (PIC) and an electronic integrated circuit (EIC), the PIC comprising an electro-absorption modulator (EAM) electrically connected to a first landing pad at a surface of the PIC, the EIC comprising an electrical component electrically connected to a second landing pad at a surface of the EIC, the method comprising:

• providing a copper pillar in the EIC contacting the second landing pad, the copper pillar protruding from the EIC;
• and
• attaching a protruding portion of the copper pillar to the first landing pad to provide an electrical interconnect between the EAM and the electrical component while stacking the EIC on the PIC such that, when viewed from the EIC towards the PIC, the EAM of the PIC is offset from the first landing pad, and
• wherein, when viewed from the EIC towards the PIC, a center of the EAM is offset from a nearest edge of the first landing pad by a distance large enough to limit a parasitic capacitance between the first landing pad and the EAM to be less than a pre-determined threshold level of tolerance, and wherein the pre-determined threshold level of tolerance is where the parasitic capacitance causes the EAM to lose modulation fidelity.

A system-in-package comprising:

• a photonic integrated circuit (PIC) comprising an electro-absorption modulator (EAM) electrically connected to a first landing pad at a surface of the PIC;
• an electronic integrated circuit (EIC) stacked on the surface of the PIC, the EIC comprising an electrical component electrically connected to a second landing pad at a surface of the EIC facing the surface of the PIC;
• and
• a copper pillar physically connecting the first landing pad to the second landing pad,
• wherein the first landing pad, the copper pillar, and the second landing pad provide at least a portion of an electrical interconnect between the EAM and the electrical component, and when viewed from the EIC towards the PIC, a center of the EAM of the PIC is offset from a nearest edge of the first landing pad by a distance large enough to limit a parasitic capacitance between the first landing pad and the EAM to less than a pre-determined threshold level of tolerance, and wherein the pre-determined threshold level of tolerance is where the parasitic capacitance causes the EAM to lose modulation fidelity.