Interconnect structure and methods thereof

A semiconductor device, comprising:

• a first dielectric layer formed over a gate stack and a contact metal layer formed over each of a source region and a drain region disposed on opposing sides of the gate stack, wherein the first dielectric layer includes a first oxide layer in contact with the gate stack;
• and
• a metal layer that electrically connects the contact metal layer over the source region to the contact metal layer over the drain region, wherein a middle portion of the metal layer is electrically isolated from the gate stack by the first dielectric layer, wherein end portions of the metal layer contacting the source region and the drain region are laterally separated from the first dielectric layer by sidewall spacers disposed on sidewalls of the gate stack, and wherein the sidewall spacers include a second oxide layer that has a same composition as the first oxide layer;
• wherein a first top surface of the gate stack defines a first plane, wherein a second top surface of the contact metal layer over the source region defines a second plane substantially coplanar with the first plane;
• and wherein a third top surface of the contact metal layer over the drain region defines a third plane substantially coplanar with both the first plane and the second plane.

A semiconductor device, comprising:

• a first gate stack and a second gate stack including source/drain regions disposed on either side of each of the first and second gate stacks, wherein the first gate stack has a first width and the second gate stack has a second width;
• a first dielectric layer formed over the first gate stack and a second dielectric layer, separate from the first dielectric layer, formed over the second gate stack, wherein the first dielectric layer has a third width that is substantially equal to the first width, and wherein the second dielectric layer has a fourth width that is substantially equal to the second width;
• and
• a local interconnect that electrically connects one of the source/drain regions disposed on either side of the first gate stack to one of the source/drain regions disposed on either side of the second gate stack, wherein the local interconnect is separated from the first gate stack by the first dielectric layer and from the second gate stack by the second dielectric layer;
• wherein first portions of the local interconnect disposed over the one of the source/drain regions disposed on either side of the first gate stack and the one of the source/drain regions disposed on either side of the second gate stack have first bottom surfaces that are substantially level with second bottom surfaces of the first dielectric layer and the second dielectric layer, and wherein a second portion of the local interconnect disposed over the at least one of the first gate stack and the second gate stack has a third bottom surface that is substantially level with top surfaces of the first dielectric layer and the second dielectric layer.