Memory device determining target resistance states

A memory device comprising:

• a plurality of first wiring lines, each extending in a first direction;
• a plurality of second wiring lines, each extending in a second direction intersecting the first direction;
• a plurality of memory cells connected between the plurality of first wiring lines and the plurality of second wiring lines, each of which includes a resistance change memory element capable of exhibiting a first resistance state and a second resistance state having a higher resistance than that of the first resistance state, and a switching element connected in series with the resistance change memory element and having a characteristic of changing from an off state to an on state when a voltage applied between two terminals thereof increases and reaches a first voltage, and changing from an on state to an off state when a voltage applied between the two terminals decreases and reaches a second voltage that is lower than the first voltage;
• and
• a determination operation control circuit that controls a determination operation of a resistance state of the resistance change memory element included in a selected memory cell of the plurality of memory cells connected between a selected first wiring line of the plurality of first wiring lines and a selected second wiring line of the plurality of second wiring lines, wherein
• the determination operation control circuit is configured to:
• during a first read period, set the switching element included in the selected memory cell to an on state by changing a voltage of the selected first wiring line at a first on-state setting time point while the selected second wiring line is set to a floating state, and acquire a first preliminary determination target voltage applied between the selected first wiring line and the selected second wiring line at a first preliminary determination target voltage acquisition time point at which a first elapsed time has elapsed from the first on-state setting time point;
• during the first read period, set the switching element included in the selected memory cell to an on state by changing a voltage of the selected first wiring line at a second on-state setting time point while the selected second wiring line is set to a floating state, and acquire a second preliminary determination target voltage applied between the selected first wiring line and the selected second wiring line at a second preliminary determination target voltage acquisition time point at which a second elapsed time that is different from the first elapsed time has elapsed from the second on-state setting time point;
• during a write period after the first read period, set a reference resistance state selected from the first resistance state and the second resistance state to the resistance change memory element included in the selected memory cell;
• during a second read period after the write period, set the switching element included in the selected memory cell to an on state by changing a voltage of the selected first wiring line at a third on-state setting time point while the selected second wiring line is set to a floating state, and acquire a first preliminary reference voltage applied between the selected first wiring line and the selected second wiring line at a first preliminary reference voltage acquisition time point at which the first elapsed time has elapsed from the third on-state setting time point;
• during the second read period, set the switching element included in the selected memory cell to an on state by changing a voltage of the selected first wiring line at a fourth on-state setting time point while the selected second wiring line is set to a floating state, and acquire a second preliminary reference voltage applied between the selected first wiring line and the selected second wiring line at a second preliminary reference voltage acquisition time point at which the second elapsed time has elapsed from the fourth on-state setting time point;
• and
• determine, based on a voltage difference between a determination target voltage obtained by adding the first preliminary determination target voltage and the second preliminary determination target voltage and a reference voltage obtained by adding the first preliminary reference voltage and the second preliminary reference voltage, a determination target resistance state that was set in the resistance change memory element included in the selected memory cell prior to the first read period.